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pentium/p54c pci/isa chipset preliminary v2.0 april 2, 1995 1 silicon integrated systems corporation 1 5501/5502/5503 overview sis5501 pci/isa cache memory controller ( pcmc ) SIS5502 pci local data buffer ( pldb ) sis5503 pci system i/o ( psio ) a whole set of the sis5501, 5502, and 5503 provides fully integrated support for the pentium/p54c pci/isa system. the chipset is developed by using a very high level of function integration and system partitioning. with the sis5501, SIS5502, and sis5503 chipset, only 12 ttls (include 3 dram address buffer) are required to implement a low cost, high performance, pentium/p54c pci/isa system. figure 1 shows the system block diagram. address data address/data address data 373 pentium , p54c 502 pci local device #1 pci local device #2 isa device #1 isa device #2 503 245 host bus pci bus isa bus sram cpu pldb pcmc psio 501 244 dram xd bus * * * * * * 5 5 5 ide drives ide buffers figure 1.1 system block diagram
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 2 silicon integrated systems corporation 2. sis5501 2.1 features ? ? ? ? supports the 510\60, 567\66, 735\90, 815\100 mhz and 75 mhz pentium processor ? ? ? ? supports m1 and other pentium compatible cpu ? ? ? ? supports the pipelined address mode of the pentium or the p54c processor ? ? ? ? integrated second level ( l2 ) cache controller - write through and write back cache modes - 8 bits or 7 bits tag with direct mapped organization - supports standard and burst srams - supports 64 kbytes to 2 mbytes cache sizes - cache read/write cycle of 3-2-2-2 or 4-2-2-2 using standard srams at 66 mhz - cache read/write cycle of 3-1-1-1 using burst srams at 66 mhz ? ? ? ? integrated dram controller - supports 8 banks of simms up to 512 mbytes of cacheable main memory - supports " table- free " dram configuration - concurrent write back - cas#-before-ras# transparent dram refresh - supports 256k/512k/1m/2m/4m/16m xn 70ns fast page mode and edo dram - the fastest burst cycle speed for fp and edo are 6-3-3-3 and 6-2-2-2 respectively - programmable cas# driving current - programmable dram speed ? ? ? ? two programmable non-cacheable regions ? ? ? ? option to disable local memory in non-cacheable regions ? ? ? ? shadow ram in increments of 16 kbytes ? ? ? ? supports pentium/p54c smm mode ? ? ? ? supports cpu stop clock ? ? ? ? provides high performance pci arbiter - supports four pci masters - supports rotating priority mechanism - hidden arbitration scheme minimizes arbitration overhead ? ? ? ? integrated pci bridge - translates the cpu cycles into the pci bus cycles - provides cpu-to-pci read assembly and write disassembly mechanism - translates sequential cpu-to-pci memory write cycles into pci burst cycles - pci burst write in the pace of x-2-2-2-.... - pci burst read l2 cache in x-2-2-2-.... - pci burst read dram in x-3-2-3-2-.... - cache snoop filters ensure data coherency and minimize snoop frequency - meet pci specification buffer strength ? ? ? ? 208-pin pqfp package ? ? ? ? 0.6m cmos technology
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 3 silicon integrated systems corporation 2.2 functional block diagram ha[31:3] hbe[7:0]# ads# m/io# w/r# d/c# cache# brdy# cpuhold cpuhlda hitm# a20m# ken# eads# na# cpurst init tag[7:0] alt altwe# tagwe# ka4x ka3/ka4y krex#/ coe0# krey#/ coe1# kwex# kwey # cale adsc#/ adsv# kce[7:0]#/ cwe[7:0] # ras[3:0]# cas[7:0]# ramw# ma[11:0] cpu interface c/be[3:0]# ad[31:0] frame# irdy# trdy# devsel# stop# par serr# req[3:0]# gnt[3:0] plock# pciclko pciclki pcirst# pci interface hcr[1:0] adle# adoe mdle cmpsh cmpop cppsh cppop prdle hgdw parity# 502 buffer control smout wakeup[1:0] smi# smiact# stpclk# sioreq# siognt# kbrst#/break# turbo# osc aclk clk pwrgd dram contro pmu & misc. cache control sis5501 functional block diagram *ras[7:4]# 5 l * : multi-function pin flush#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 4 silicon integrated systems corporation 2.3 general description the sis5501(pcmc) bridges between the host bus and the pci local bus. the sis5501 (pcmc) monitors each cycle initiated by the cpu, and forwards it to the pci bus if the cpu cycle does not target the local memory. for the cpu or the pci bus to the local memory cycles, the built-in cache and dram controller assume control to the secondary cache, drams, and the SIS5502 (pldb). the sis5501 (pcmc) also guides the SIS5502 (pldb) for correct data flow. all of the green pc functions are provided. 2.4 cpu interface the sis5501 is designed to support pentium/p54c cpu host interface at 66.667/60/50 mhz. the host data bus and the dram bus are 64-bit wide. the sis5501 supports the pipelined addressing mode of the pentium/p54c cpu by issuing the next address signal, na#. na# is only generated in two cases: a) burst read l2 cache or dram, and b) single read dram. the pcmc supports the cpu l1 write back(wb) or write through(wt) cache and the pcmc l2 wb or wt cache. the l1 cache is snooped by the assertion of eads# when the cpu is put in the hold state. the pcmc issues cpuhold to the pentium/p54c cpu in response to the assertion of pci master requests(req[3:0]#, and sioreq#). upon receiving the cpuhlda from the cpu, it does not immediately assert gnt[3:0]# or siognt# until both the cpu to pci posted write buffer and the memory write buffer are empty. during inquire cycles, the cpuhold may be negated temporarily to allow the cpu to write back the inquired hit modified line to l2 or dram. 2.5 cache controller the built-in l2 cache controller uses a direct-mapped, bank-interleaved/non-interleaved scheme, which can be configured as either in the write through or write back mode. both standard and burst srams are supported. table 1 shows the cache sizes that are supported by the sis5501, with the corresponding tag ram sizes, data ram sizes, and cacheable memory sizes. tables 2 and 3 summarize the performance and options when either the standard srams or the burst srams are used.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 5 silicon integrated systems corporation table 1 cache size data ram tag ram alter ram cacheable size interleaved 64k 8kx8x8 2kx8 2kx1 16m no 128k 8kx8x16 4kx8 4kx1 32m yes 256k 32kx8x8 8kx8 8kx1 64m no 512k 32kx8x16 16kx8 16kx1 128m yes 512k 64kx8x8 16kx8 16kx1 128m no 1m 128kx8x8 32kx8 32kx1 256m no 1m 64kx8x16 32kx8 32kx1 256m yes 2m 128kx8x16 64kx8 64kx1 512m yes the pcmc also provides an alternative to save the dirty sram chip. this is accomplished by sharing the alter bit with tag address bits in the same 8-bit wide tag ram. system uses this implementation supports 7 tag address bits and 1 dirty bit. by doing so, the cacheable local memory sizes are reduced to half of the original sizes as indicated in table 1. in reality, the l2 cacheable dram size is determined by: 1) max. l2 cacheable size as described in table 1. 2) non-cacheable area defined in register 57h, 58h, 59h and 5ah and 3) c, d, e, f segment cachability defined in register 53h, 54h, 55h, and 56h. but, the l1 cacheable size is only determined by 2), 3), and the maximum dram size, i.e., 512m bytes. thus, the cycles with address ranging over the l2 cacheable size but within the 512m bytes can also be cacheable to l1. the behavior of ken# is ruled by the l1 cacheability. note that only code of c, d, e, f segment is cacheable to l1/l2, and the data portion of c, d, e, f segment is not cacheable to l1/l2. table 2 burst sram speed setting cycle type 66,60 mhz 50mhz burst read 3/ 4 -1-1-1 3/4-2-2-2 3/ 4 -1-1-1 3/4-2-2-2 burst write 3/ 4 -1-1-1 3/4-2-2-2 3/ 4 -1-1-1 3/4-2-2-2 single read 3/ 4 3/ 4 single write 3/ 4 3/ 4 note : 1: the burst sram speed for 66/60 mhz is 9 ns. for 50mhz, it is 12 ns. 2: x -y-y-y is the recommended setting.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 6 silicon integrated systems corporation table 3 asynchronous sram speed setting (apply to read and write cycle) 66 mhz 60 mhz 50mhz cache configuration tag data tag data tag data 3-1-1-1 interleave --- --- --- --- 15ns 15ns 3-1-1-1 non-interleave --- --- --- --- --- --- 3-2-2-2 interleave 15ns 15ns 15ns 15ns 20ns 20ns 3-2-2-2 non-interleave 15ns 15ns 15ns 15ns 20ns 20ns 3-3-3-3 interleave 15ns 15ns 15ns 15ns 20ns 20ns 3-3-3-3 non-interleave 15ns 15ns 15ns 15ns 20ns 20ns 4-1-1-1 interleave 15ns 12ns 15ns 12ns 20ns 15ns 4-1-1-1 non-interleave --- --- --- --- --- --- 4-2-2-2 interleave 15ns 15ns 20ns 20ns 20ns 20ns 4-2-2-2 non-interleave 15ns 15ns 20ns 20ns 20ns 20ns 4-3-3-3 interleave 15ns 20ns 20ns 20ns 20ns 20ns 4-3-3-3 non-interleave 15ns 20ns 20ns 20ns 20ns 20ns 5-1-1-1 interleave 20ns 12ns 20ns 12ns 20ns 15ns 5-1-1-1 non-interleave --- --- --- --- --- --- 5-2-2-2 interleave 20ns 15ns 20ns 20ns 20ns 20ns 5-2-2-2 non-interleave 20ns 15ns 20ns 20ns 20ns 20ns 5-3-3-3 interleave 20ns 20ns 20ns 20ns 20ns 20ns 5-3-3-3 non-interleave 20ns 20ns 20ns 20ns 20ns 20ns 2.6 dram controller the 5501 can support 8 rows of dram, and memory size from 2 mbytes up to 512 mbytes. each populated bank could be single or double sided 64 bits fp dram or edo ( extended data output) dram. it is also permissible to mix fp dram bank and edo dram bank without any order. the installed dram type can be 256k x 36, 512k x 36, 1m x 36, 2m x 36, 4m x 36 or 16m x 36 simms. however, since ras 5 shares the same signal of ma 11, bank 5 should be excluded if 16 m x 36 dram is used. dbr 8~0 ( dram boundary register, register 79h and 77h~70h) are used to configure the total amount of memory. in dbr 7~0, bit 7~0 corresponds to host address 28~21 and dbr 8 bit 7~0 is used to compare against the host address 29 of bank 7~0. contents in these registers reflect the boundary address, that means the value programmed to the last dbr will be the dram size in the system. dbr0 ( reg. 70) = total amount of memory in bank 0 dbr1 ( reg. 71) = total amount of memory in bank 0 + bank 1 dbr2 ( reg. 72) = total amount of memory in bank 0 + bank 1 + bank 2 ........................................................................................................................ dbr7 ( reg. 77) = total amount of memory in bank 0 + .............+ bank 7
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 7 silicon integrated systems corporation the following 2 examples show how the dbr registers be used to determine the memory size. example 1: the system memory is populated as 2 banks of single-sided 1m x 36 dram, which are located at bank 1 and 3. this yields 16 m bytes dram totally. the dbr registers are programmed as follows: dbr0 = 00h dbr 8 bit 0 = 0 ; empty ; 0 m byte totally dbr1 = 04h dbr 8 bit 1 = 0 ; 8 m bytes for bank 1 ; 8 m bytes totally dbr2 = 04h dbr 8 bit 2 = 0 ; empty ; 8 m bytes totally dbr3 = 08h dbr 8 bit 3 = 0 ; 8 m bytes for bank 3 ; 16 m bytes totally dbr4 = 08h dbr 8 bit 4 = 0 ; empty ; 16 m bytes totally dbr5 = 08h dbr 8 bit 5 = 0 ; empty ; 16 m bytes totally dbr6 = 08h dbr 8 bit 6 = 0 ; empty ; 16 m bytes totally dbr7 = 08h dbr 8 bit 7 = 0 ; empty ; 16 m bytes totally example 2: the system memory is populated as 4 banks of single-sided 16 m x 36 dram, which are located from bank 0 to 3. this yields 512 m byte dram totally. the dbr registers are programmed as follows: dbr0 = 40h dbr 8 bit 0 = 0 ; 128 m bytes for bank 0 ; 128 m bytes totally dbr1 = 80h dbr 8 bit 1 = 0 ; 128 m bytes for bank 1 ; 256 m bytes totally dbr2 = c0h dbr 8 bit 2 = 0 ; 128 m bytes for bank 2 ; 384 m bytes totally dbr3 = 00h dbr 8 bit 3 = 1 ; 128 m bytes for bank 3 ; 512 m bytes totally dbr4 = 00h dbr 8 bit 4 = 1 ; empty ; 512 m bytes totally dbr5 = 00h dbr 8 bit 5 = 1 ; empty ; 512 m bytes totally dbr6 = 00h dbr 8 bit 6 = 1 ; empty ; 512 m bytes totally dbr7 = 00h dbr 8 bit 7 = 1 ; empty ; 512 m bytes totally the 12-bit multiplexed row/column address ma[11:0] allows the pcmc to support 256k, 1m, 4m, and 16m 70ns fast page mode drams. table 4. shows the corresponding request address bits used in column address and row address for the dram.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 8 silicon integrated systems corporation table 4. ma generation table body type 256k 512k 1m 2m 4m 16m ma cas ras cas ras cas ras cas ras cas ras cas ras ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma1 0 ma1 1 a3 a4 a5 a6 a7 a8 a9 a10 a11 na na na a12 a13 a14 a15 a16 a17 a18 a19 a20 na na na a3 a4 a5 a6 a7 a8 a9 a10 a11 na na na a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 na na a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 na na a22 a13 a14 a15 a16 a17 a18 a19 a20 a21 na na a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 na na a22 a13 a14 a15 a16 a17 a18 a19 a20 a21 a23 na a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 na a22 a24 a14 a15 a16 a17 a18 a19 a20 a21 a23 na a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a22 a24 a26 a15 a16 a17 a18 a19 a20 a21 a23 a25 to improve the cpu write drams performance, there is a one level built-in cpu-to-memory posted write buffer with 4 qws deep (ctmpb). all the single writes and the burst writes are buffered. in the cpu read miss/line fill cycle, the write-back data from the l2 cache are also buffered into the ctmpb. at the same time, the pcmc starts reading from the drams. the buffered data are written to the drams when the read cycle completes. with this concurrent write back policy, many wait states are eliminated. however, any other cycle targeting the drams will be suspended until the ctmpb is empty. table 5 outlines the read and write dram cycle performance based on 70ns drams. table 5 dram performance cycle type 66,60 mhz 50mhz dram type read (page hit/row miss /page miss) 6/9/12-3-3-3 7/10/13-4-4-4 6/9/12-2-2-2 7/10/13-2-2-2 6/9/12-3-3-3 7/10/13-4-4-4 6/9/12-2-2-2 7/10/13-2-2-2 standard page mode standard page mode edo edo posted write (cpu --> buffer) 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 standard page mode, edo standard page mode, edo standard page mode, edo write retire rate (buffer --> dram) 3 /4/5 2 3 /4/5 2 standard page mode edo note: 1: x-y-y-y is the recommended setting.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 9 silicon integrated systems corporation table 6 dram speed setting based on 70ns drams (apply to read and write cycle) register 66mhz 60mhz 50mhz read cas pulse width 50h bit 7-6 2t 2t 2t write cas pulse width 50h bit 5 2t 2t 2t cas precharge time 1 53h bit 7 1t/2t 1t/2t 1t ras precharge time 53h bit 1 4t 4t 4t ras to cas delay time 53h bit 2 3t 3t 3t refresh ras active time 52h bit 0 5t 5t 4t dram write push to cas delay 5bh bit 3 1t 1t 1t edo dram cas pulse width 2 7ch bit 1 1t/2t 1t/2t 1t edo dram cas precharge time 2 7ch bit 0 1t/2t 1t/2t 1t note: 1. the burst dram read hit cycle is 6-3-3-3 when the cas precharge time is 1t. if the cas precharge time is 2t, the burst dram read hit cycle is increased to 7-4-4-4. 2. when edo type drams are installed and register 7ch bits[1:0] are set to "11" (1t), the burst dram read hit cycle is 6-2-2-2. the standard fast page mode dram timing is applied, if register 7ch bits[1:0] are set to "00". in fact, 5501 can detect the edo type dram and applies optimal timing automatically. 2.7 pci arbiter the sis5501 contains a high performance hidden arbitration scheme that allows efficient bus sharing among five pci masters and the cpu. note that one pci master is reserved for the psio chip. the sis5501 employs the priority rotation scheme that is done at two different layers. the first layer is shared between psio and four pci masters as a group. the second layer consists of four pci masters with equal priority. arbitration is done at both layers. the winner of arbitration among the four pci masters arbitrates the pci bus against psio. fair rotation scheme applies only at layer level. the arbitration scheme assures that isa master or dma channels (represented by psio) access the bus with minimal latency. the psio is given a high level of priority to assure compatibility with traditional isa expansion boards that require short bus latency. this implementation together with pci programmable bursting address counter guarantees isa device will not be starved during pci master long bursting cycle. for example, when the maximum bursting length is 512 bytes, the maximum arbitration latency for psio, and pci master is about 12us, and 40us respectively. the following two figures detail the rotation arbitration structure and its corresponding timing diagram.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 10 silicon integrated systems corporation rotation arbitration scheme: bus grant priority g0123 g01 g23 g0 g1 g2 g3 sw1 sw2 sw3 sw4 g4 notation: sw1: is the switch for path from node g4 or g0123 to bus grant priority sw2: is the switch for path from node g01 or g23 to node g0123 sw3: is the switch for path from node g0 or g1 to node g01 sw4: is the switch for path from node g2 or g3 to node g23 g01, g23, g0123: are intermediate nodes g4: is the bus request from psio g0, g1, g2, g3: are the bus requests from pci device 0, device 1, device 2, device 3 respectively. initial path parking: sw1 : bus grant priority-g4 sw2 : g0123-g01 sw3 : g01-g0 sw4 : g23-g2 rule of rotating priority for bus arbitration: ? bus grant priority will choose a path whenever it encounters an optional path. ? pci bus will be granted as daisy chain ? path switches will be toggled from bus grant priority to any request node (g4, g0, g1, g2, g3) if any of them have been utilized example: initial priority: g4, g01, g0, g2 1. psio(g4) request bus siognt# is asserted sw1 is toggled to g0123 (since it has been utilized) priority change to g0, g1, g2, g3, g4
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 11 silicon integrated systems corporation 2. psio, req3, req2, req1, req0 are requesting bus gnt0# is asserted sw1, sw2 and sw3 are toggled to g4, g23 and g1 respectively (since they have been utilized) priority change to g4, g2, g3, g1, g0 3. req3, req2, req1, req0 are active gnt2# is asserted sw2, sw4 are toggled to g01 and g3 respectively (since they have been utilized) priority change to g4, g1, g0, g3, g2 4. req3, req2, req1, req0 are active gnt1# is asserted sw2, sw3 are toggled to g23 and g0 respectively (since they have been utilized) priority change to g4, g3, g2, g0, g1 5. req3, req2, req1, req0 are active gnt3# is asserted sw2, sw4 are toggled to g01 and g2 respectively (since they have been utilized) priority change to g4, g0, g1, g2, g3 6. during 3-5 if there is a request comes from psio, the arbiter will grant bus to psio. pci arbiter - rotation arbitration scheme f0 febd7e 501arbi note : hold is internal signal cpuclk pciclk req[3:0]# sioreq# gnt[3:0]# siognt# hold cpuhold cpuhlda hlda frame# irdy# a pci master can burst so long as the target can source/sink the data, and no other agent requests the bus. however, pci specifies two mechanisms that cap a master's tenure in the presence of other requests, so that predictable bus acquisition latency can be achieved. one is the master latency timer(lt) that is not implemented into the pcmc, the other is the target
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 12 silicon integrated systems corporation initiated termination. in the sis5501, a programmable bursting address counter(pbac) is implemented to disconnect the pci master during the long bursting cycle. in this way, high throughput is maintained, and the bus latency is still kept reasonably small. note that the bursting length is naturally applied to pci master to local memory accessing. when pci master accesses non-local memory target, the master and target should together have the responsibility of maintaining reasonable latency, but not the system arbiter does. the pci arbiter asserts only one gnt# at any time. the 5501 has also implemented a time-out counter to prevent faulty device hugging the bus. if the pci bus is granted to a pci device and the bus is currently idle, 16 pci clocks is the limitation that device should assert frame# during the period of time. if time-out occurs, the arbiter will mask request line, therefore desserts gnt#. when this happens, all pci devices start arbitration again. note that psio is free to this constraint. the 5501 pci master will also mask the psio request to the arbiter if the pci lock# is asserted to keep isa master or dma channels target latency within specification. the 5501 pci arbiter is also allowed to force system back to cpu each time after sioreq# is serviced. this function is disabled by default, and can be enabled by set bit 7 of register 6f in the pcmc configuration space. 2.8 pci bridge 2.8.1 pci master controller the pci master controller forwards the cpu cycles not targeting the local memory to the pci bus. in the case of a 64-bit cpu request or a misaligned 32-bit cpu request, the pcmc assumes the read assembly and write disassembly control. a 4 level posted write buffer (ctppb) is implemented to improve the cpu to pci memory write performance. except for on-board memory write cycles, any cycles forwarded to the pci bus will be suspended until the ctppb is empty. for pci bus memory write cycles, the cpu data are pushed into the ctppb if it is not full. the pushed data are, at later time, written to the pci bus. if the consecutive written data are in dw incremental sequence, they will be transferred to the pci bus in a burst manner. the burst transfer rate is always x-2-2-2-... until 128 dws are exhausted. the pci master interface can read data from or write data to the pci bus at the utmost speed of 1 wait state. this is due to the fact that the pcmc drives the pci bus address and the pldb drives the pci bus data. that necessitates a turn around cycle between the address and the data phases. the pcmc provides a mechanism for converting standard i/o cycles on the cpu bus to configuration cycles on the pci bus. configuration mechanism #1 in pci specification 2.0 page 61 is used to do the cycle conversion. the pcmc always intercepts the first interrupt acknowledge cycle from cpu bus, and forwards the second interrupt acknowledge cycle onto the pci bus.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 13 silicon integrated systems corporation 2.8.2 pci slave controller the sis5501 operates as a slave on the pci bus whenever a pci master requests an access to the sis5501 resource such as cache, dram and the sis5501 internal registers. note that the internal registers can only be accessed by the sis5501 itself when in cpu cycle. in the sis550x pci/isa system, the cpu is placed in hold state before granting the pci bus to a pci master. the following figure shows the behavior of cpuhold/cpuhlda in response to pci masters requests. only linear ordered pci cycles are supported by the pcmc pci slave interface. 501 drives ha 501 park pci master drives ad 501 park note : hold,cip# (current in progress) are internal signal 501req cpuclk pciclk req# hold cpuhold cpuhlda hlda gnt# frame# irdy# cip# ha ad a pci master to the local memory access is not conducted until the snoop cycle has completed. the snoop cycle is used to inquire the first level cache to maintain coherency between first level and second level caches and main memory. snoop cycles are performed by driving the pci master address onto the cpu bus and asserting eads#. depending on the status of hitm# two clocks after the assertion of eads#, pcmc conducts the pci master cycles as table 8 outlines.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 14 silicon integrated systems corporation table 7 pci master read cycle l1 l2 data transfer miss (or unmodified) miss data transfer from dram to pci miss (or unmodified) hit (dirty or !dirty) data transfer from l2 to pci hitm miss data is first written back from l1 to dram. then, pci master gets data from dram. hitm hit (dirty or !dirty) data is first written back from l1 to l2. then, pci master gets data from l2. the line is marked dirty in the l2. pci master write cycle l1 l2 data transfer miss (or unmodified) miss data transfer from pci to dram miss (or unmodified) hit (dirty or !dirty) data transfer from pci to dram and l2. the dirty bit is not changed. hitm miss data is first written back from l1 to dram. then, pci master writes data to dram. hitm hit (dirty or !dirty) data is first written back from l1 to l2. then, pci master writes data to l2 and dram. the line is marked dirty in the l2. a snoop filter is implemented to prevent the need of multiple inquires to the same line if the line was inquired previously. to support snoop filter, a snoop address latch (sal) and a line comparator are implemented. the line comparator is used to determine if the new address (na) is the same as the content of the sal. if it is not, the na is loaded into the sal, and a snoop cycle is issued. in addition, a valid bit in association with the sal is used to ensure the snoop filtering is effective only when hlda is asserted. the simplified filter algorithm is: 1) write back mode a) if na=sal in a pci master write cycle, the pcmc only issues eads#. it does not wait for the status of hitm#. b) if na=sal in a pci master read cycle, no snoop cycle nor eads# is issued. c) if na sal in a pci master cycle, the pcmc issues a snoop cycle by eads#, and then monitors the status of hitm#. d) during a burst transaction, the pcmc automatically generates a snoop cycle when the address advances across a new line. 2) write through mode in the following two cases, the pcmc only generates eads#. it ignores the logic of hitm#. a) if na=sal in a pci master write cycle, and b) during a burst transaction, the address advances across a new line.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 15 silicon integrated systems corporation in the sis550x, the inv signal of p54c should be connected to w/r# that is driven by the sis5501 in the pci master cycle. in this way, the sis5501 can invalidate the line that is currently inquired via the assertion of eads# in the pci master write cycles. the pcmc slave interface supports pci burst transfers. a burst transfer will be disconnected (retry) if the transfer goes across the 512 bytes(or 1 kbytes selected by register 5dh, bit 5) address boundary. this is due to the fact that the address generator, to support the burst transfer, can only address 512 or 1k bytes. in this way, at most 32 cache lines can be uninterruptedly transferred if they are in i, s, or e state in the l1 cache. another reason for the constraint is that page miss may occur only once during the entire bursting transaction since the maximum bursting length is always within the page size in any of the used dram . the pci master writes are buffered in the one qw deep pci to memory posted write buffer (ptmpb). the pcmc always packs an aligned qw pci write data into the write buffer, and then retires it into the dram array or the l2 cache. the pci master write performance, to the utmost, is x-2-2-2- ... the pci master reads are through a qw read buffer with which the burst transfers can perform in the pace of x-2-2-2-... (from the l2 cache), or x-3-2-3-2-... (from the drams). concurrent refresh will still be performed when cpu is put into hold state. if the dram is idle, refresh can be conducted at any time. if refresh request occurs at the same time that a pci master wants to access dram, an arbitration scheme is employed to resolve the conflict. the refresh request may thus get service while the pci master accessing is suspended until refresh cycle is completed. although refresh may win the dram bus, at most one refresh cycle may be conducted for each individual pci transaction, i.e. for each frame# initiating. on the other hand, refresh may be also deferred until the dram is idle. in sis550x system, the refresh may be postponed for no more than 24 us in the worst case when a pci master is reading the whole 32 lines through one burst transaction. 2.8.3 pci bus speed setting the following settings apply to all system environment, even though the system is running at 66mhz while the pci bus is running at 33mhz.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 16 silicon integrated systems corporation table 8 pci bus setting register setting unit latency from ads# to monitor local memory status 5ch bit 7 2t cpuclk cas# pulse width in pci master write cycle 5ch bit 4 1t pciclk latency from the disarming of "full" to the assertion of brdy# for the pending cpu to pci write cycle 5ch bit 3 1t cpuclk latency from reading l2/dram to the assertion of trdy# in pci master read cycles 5dh bit 4 1t pciclk latency from packing one qword into ptmpb to the assertion of cas#(or kwe#) 5dh bit 3 1t pciclk latency from trdy# to brdy# in cpu read/write pci slave cycles 5dh bit 2 2t cpuclk 2.9 green pc function the following paragraphs are the pmu ( power management unit ) features description: 2.9.1 power states the pmu provides different power management states, which are described in the following sections. (i) monitor standby state the monitor will be blanked and the external devices are turned off through smout when the monitor standby timer expires. monitor standby monitors the following events: irq 1-15 hold nmi each irq has two sets of mask bits, one for wake up mask, and the other for standby mask. the hold includes the pci local masters and the isa master request. each event is maskable. if no event happens during the monitored period and the timer expires, an smi is generated and the monitor enters the standby state. once the monitor is in the standby state, any event from irq1-15, nmi or hold will cause an smi which brings the monitor back to the normal state. the time slot of the monitor standby timer is programmable to 6.6sec, 0.84sec, 13.3ms, 1.6ms. (ii) system standby state
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 17 silicon integrated systems corporation if the system standby timer expires, an smi is generated for the system to enter the system standby state. the following events happen: stpclk# is asserted to stop the cpu clock the hard disk drives spindle motors can be turned off the serial, parallel ports or the programmable i/o port can be turned off once the stpclk# is asserted, any events from irq1-15, nmi, hold, init will cause the stpclk# be de-asserted. if any of the hard disk motors, serial, parallel or programmable i/o ports were turned off, they will be back to the normal state only when they are accessed. system standby monitored events (each event is maskable) programmable i/o ports (one is a 10-bit i/o port, another is a16-bit i/o port) irq 1-15 (each has 2 sets of mask bits as for monitor standby state) hold nmi hard disk ports ( 1f0-1f7h, 3f6-3f7h, 170-17fh, 320-32fh) serial ports ( 2f8-2ffh, 3f8-3ffh, 2e8-2efh, 3e8-3efh) parallel ports ( 278-27fh, 378-37fh, 3bc-3beh) a0000-affffh or b0000-bffffh address trap (video ram) c0000-c7fffh address trap (video bios) 3bx-3dxh (video i/o port) the time slot of the system standby timer is programmable to 9 sec, 1.1 sec, 70ms, and 8.85ms. (iii) throttling state in throttling state, stpclk# is asserted and de-asserted periodically. this function is maskable. the throttling timer (registers 61h and 62h) is programmable and the time slot is 35us. 2.9.2 break switch smi whenever the break switch is pressed, it caused an smi to enter or leave power saving state. the signal from the break switch is a level trigger signal which lasts for more than 3 cpu clocks. 2.9.3 software smi if the software smi enable bit is set and a '1' is written to bit 1 of register 60h, an smi# is generated and the software smi service routine is invoked. the bit 1 of register 60h should be cleared at the end of the smi handler. 2.9.4 shadow register in order to support "suspend to hdd" function, all necessary shadow registers are implemented into 5503. for more detailed information, please refer to "5503 register description"
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 18 silicon integrated systems corporation 2.10 configuration registers there are two sets of registers in the pcmc, i/o mapped registers and the pci configuration space registers. 2.10.1 i/o mapped registers the sis5501 uses pci configuration space access mechanism #1. this mechanism defines two registers, config_address (cf8h) register and config_data (cfch) register. both config_address and config_data are read/write registers, and the length is dword. the mechanism is to write a value into config_address first, then read or write to config_data. the write to config_address specifies the pci bus, device on that bus, and the configuration register in that device being accessed. the read or write to config_data will cause the host bridge to translate the config_address value to the requested configuration cycle. the definition of config_address register is described below: register 0cf8h config_address register reserved bus number device number function number register number 0 0 0 1 2 7 8 10 11 15 16 23 24 30 31 enable bit ('1' = enabled, '0' = disabled) bit 31 is an enable flag for determining if the accesses to config_data should be translated to configuration cycles on the pci bus. bits 30:24 reserved, read only, and must return 0's when read. bits 23:16 choose a specific pci bus in the system. bits 15:11 choose a specific device on the bus. bits 10:8 choose a specific function in a device. bits 7:2 choose a dword in the device's configuration space. bits 1:0 read only and must return 0's when read. a full dword i/o write to address 0cf8h, the host bridge will load the data into config_address register. also, a full dword i/o read to 0cf8h, the host bridge gets the data from config_address register. any non-dword writes or reads to 0cf8h are treated as normal pci i/o cycles. when the host bridge of sis5501 sees an i/o access that falls inside the dword beginning at config_data address, it checks the enable bit of the config_address register. if bit 31 of config_address register is 1, the i/o cycle is translated into a configuration cycle.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 19 silicon integrated systems corporation there are two types of configuration cycle determined by bus number. if the bus number is zero, the configuration cycle will be type 0. if the bus number is non-zero, the configuration cycle will be type 1. for type 0 configuration cycle, ad[1:0] is driven to "00" during the address phase of the cycle. the host bridge decodes the device number of config_address to assert only one "1" on the ad[31:11] and copies bits [10:2] of config_address to ad[10:2] directly. for instance, when accessing the configuration registers of sis5501, because 5501 is considered device 0 on bus 0, ad11 will be high, and bits[10:2] of config_address are copied to ad[10:2] directly. never use ad11 as the idsel line for any other pci target device since it is reserved for pcmc. the 5501 responds to configuration by asserting devsel#. for type 1 configuration cycle, ad[1:0] is driven to "01" and bits[31:2] of config_address are copied to ad[31:2] directly during the address phase of the cycle. the byte-enables for the data phase of both types 0 and type 1 configuration cycles are copied from the hbe[7:4]# directly. the following programming sequences is an example of writing register 51h in pcmc and of reading register 5ch, 5dh, 5eh and 5fh in pcmc. write 51h: mov eax, 80000050h out 0cf8h, eax mov al, data out 0cfdh, al read 5ch, 5dh, 5eh and 5fh: mov eax, 8000005ch out 0cf8h, eax in 0cfch register 0cf9h turbo and reset control register . bits 7:5 reserved bit 4 init enable when this bit is set to 1 ,the pcmc drives init during software reset. when this bit is cleared to 0, the pcmc drives cpurst during software reset, and init is inactive. bit 3 cpu bist enable. when this bit is set to 1 and bit 4 as well as bit 1 are enabled, a subsequent initiation of the cpu hard reset through bit 2 of this register enables the built
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 20 silicon integrated systems corporation in self test(bist) mode of the cpu. the pcmc also drives the init during the hard reset. bit 2 reset cpu. there are two types of resets to the cpu: a hard reset using the cpurst signal and a soft reset using the init signal. if bit 1 of this register is set to 1 and bit 2 transitions from 0 to 1, the pcmc initiates a hard reset. a hard reset through this register thus requires two write operations to this register: the first write operation writes a 1 to bit 1 and a 0 to bit 2. the second write operation writes a 1 to bit 1 and a 1 to bit 2. when bit 1 of this register is 0 and bit 2 transitions from 0 to 1, the pcmc initiates a soft reset. the sequence to initiate a soft reset through this register is identical to that of a hard reset except a 0 is written to bit 1 in the first write operation. bit 1 enable system hard reset. when this bit is set to 1 and bit 2 transitions from 0 to 1, the pcmc initiates a hard reset to the cpu . when this bit is 0 and bit 2 transitions from 0 to 1, the pcmc initiates a soft reset to the cpu. bit 0 select turbo /deturbo mode there are two ways to enter deturbo mode. one is through software; another is hardware. ? software deturbo: set reg. 5bh bit 1 to 1, reg. 65h bit 3 to 1, reg. 78h bit 2 to 0 and pull gnt#3 high, then set reg. cf9h bit 0 to 1. ? hardware deturbo: set reg. 5bh bit 1 to 1, reg. 65h bit 3 to 1, reg. 78h bit 2 to 0 and pull gnt#3 high, then press deturbo switch. 2.10.2 pci configuration space mapped registers register 00h vendor id - low byte bits 7:0 39h register 01h vendor id - high byte bits 7:0 10h register 02h device id - low byte bits 7:0 06h register 03h device id - high byte bits 7:0 04h register 04h command - low byte bit 7 reserved
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 21 silicon integrated systems corporation bit 6 respond to parity. this bit is always 0 since the pcmc does not support parity checking on the pci bus bits 5:4 reserved bit 3 enable special cycle. this bit is always 0 since the pcmc does not issue special cycle. bit 2 enable bus master. this bit is always 1, allowing the pcmc to serve as a pci bus master. bit 1 enable response to memory access. 0: disables pci master's accesses to local memory 1: enables pci master's accesses to local memory bit 0 enable response to i/o access. this bit is always 0 since the pcmc does not respond to any pci i/o cycles. the pcmc only responds to cpu initiated i/o cycles. register 05h command - high byte bits 7:0 reserved register 06h status - low byte bits 7:0 reserved register 07h status - high byte bit 7 detected parity error. this bit is always 0 since the pcmc does not support parity checking on the pci bus. bit 6 signaled system error. this bit is set when the pcmc asserts serr#. this bit is cleared by writing a 1 to it. bit 5 received master abort. this bit is set by the pcmc whenever it terminates a transaction with master abort. this bit is cleared by writing a 1 to it. bit 4 received target abort. this bit is set when a cpu to pci transaction is terminated with target abort. this bit is cleared by writing a 1 to it. bit 3 signaled target abort. this bit is always 0 since the pcmc will not terminate a transaction with target abort.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 22 silicon integrated systems corporation bits 2:1 devsel# timing devt. the two bits define the timing to assert devsel#. the pcmc asserts the devsel# signal within three clocks after the assertion of frame#. the default value is devt=10. in fact, the pcmc always asserts devsel# in medium timing except in cpu writes to i/o port 64h or 60h. bit 0 reserved register 08h revision identification. bits 7:0 00h. register 0b~09h class code bits 23:0 060000h register 0eh header type bits 7:0 00h register 50h bits 7:6 dram read cas pulse width 00 : 4t 01 : 3t 10 : 2t 11 : reserved bit 5 dram write cas pulse width 0 : 3t 1 : 2t bit 4 ma timing setting 0: normal operation. (md is changed on the cas# rising edge.) 1: advance 1t than normal operation. when using edo dram, this bit must set to 0. bit 3 reserved bit 2 cache toggle /linear burst mode selection 0: toggle mode 1: linear burst mode bits 1:0 dram type selection 00: 256k x n
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 23 silicon integrated systems corporation 01: 1m x n 10: 4m x n 11: 16m x n register 51h bit 7 l2 cache exist or not 0 : not exist 1 : exist bit 6 l2 cache enable 0 : disable 1 : enable bit 5 sram type ( standard or burst ) 0 : standard sram 1 : burst sram bit 4 l2 cache wt/wb policy 0 : write-through mode 1 : write-back mode bits 3:1 l2 cache size 000 : 64kb 001 : 128kb 010 : 256kb 011 : 512kb 100 : 1mb 101 : 2mb 11x : reserved bit 0 cpu l1 cache write-back enable 0 : disable 1 : enable register 52h bits 7:6 standard sram cache speed (read/write) 00 : 5-x-x-x slower 01 : 4-x-x-x faster 10 : 3-x-x-x fastest 11 : reserved
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 24 silicon integrated systems corporation bits 5:4 standard/burst sram x setting (burst read/write cycle ) 00 : 3t x1 : 1t 10 : 2t bit 3 cache interleave enable 0 : disable 1 : enable bit 2 burst sram cache burst cycle 0 : 4-x-x-x 1 : 3-x-x-x bit 1 cache sizing enable 0: normal operation 1: always cache hit to enable cache sizing for bios bit 0 refresh ras active time 0 : 6t 1 : 5t register 53h bit 7 dram cas precharge time 0 : 2t 1 : 1t bit 6 shadow ram read enable 0 : disable 1 : enable when this bit is enabled, the f segment is shadowed by default. before shadowing, bios should not turn on the bit so that reading f segment is always forwarded to pci bus. bit 5 shadow ram write protection enable 0 : disable 1 : enable after porting the shadowed segment into dram, this bit can be set so that the corresponding shadowed segment is not writable. under such circumstances, the cycle which intends to write the segment is treated as non-local memory cycle, and is forwarded to pci bus.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 25 silicon integrated systems corporation bit 4 shadow ram enable for pci master accesses 0 : disable 1 : enable bit 3 f0000h - fffffh shadow ram cacheable 0 : non-cacheable 1 : cacheable note that only code is cacheable to l2/l1 when this bit is set. bit 2 ras to cas delay time 0 : 4t 1 : 3t bit 1 ras precharge time 0 : 5t 1 : 4t bit 0 enable host to ctmpb push rate to be x-1-1-1 0 : enable 1 : disable. when this bit is disabled, the push rate is defined by bit [5:4] of register 52h. register 54h e segment setting bit 7 e0000h - e3 fffh shadow ram enable bit 6 e4000h - e7 fffh shadow ram enable bit 5 e8000h - eb fffh shadow ram enable bit 4 ec000h - e ffffh shadow ram enable bit 3 e0000h - e3 fffh shadow ram cacheable bit 2 e4000h - e7 fffh shadow ram cacheable bit 1 e8000h - eb fffh shadow ram cacheable bit 0 ec000h - e ffffh shadow ram cacheable register 55h d segment setting bit 7 d0000h - d3 fffh shadow ram enable bit 6 d4000h - d7 fffh shadow ram enable bit 5 d8000h - db fffh shadow ram enable
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 26 silicon integrated systems corporation bit 4 dc000h - d ffffh shadow ram enable bit 3 d0000h - d3 fffh shadow ram cacheable bit 2 d4000h - d7 fffh shadow ram cacheable bit 1 d8000h - db fffh shadow ram cacheable bit 0 dc000h - d ffffh shadow ram cacheable register 56h c segment setting bit 7 c0000h - c3 fffh shadow ram enable bit 6 c4000h - c7 fffh shadow ram enable bit 5 c8000h - cb fffh shadow ram enable bit 4 cc000h - c ffffh shadow ram enable bit 3 c0000h - c3 fffh shadow ram cacheable bit 2 c4000h - c7 fffh shadow ram cacheable bit 1 c8000h - cb fffh shadow ram cacheable bit 0 cc000h - c ffffh shadow ram cacheable register 57h bit 7 allocation of non-cacheable area #1 0 : local dram 1 : at bus. the local dram is disabled. bit 6 non-cacheable area #1 enable 0 : disable 1 : enable bits 5:3 size of non-cacheable area #1 (within 128 mbytes) 000 : 64kb 001 : 128kb 010 : 256kb 011 : 512kb 100 : 1mb 101 : 2mb 110 : 4mb 111 : 8mb
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 27 silicon integrated systems corporation bits 2:0 a26 ~ a24 of non-cacheable area #1 (within 128 mbytes) register 58h bits 7~0 a23 ~ a16 of non-cacheable area #1 (within 128 mbytes) register 59h bit 7 allocation of non-cacheable area #2 0 : local dram 1 : at bus. the local dram is disabled. bit 6 non-cacheable area #2 enable 0 : disable 1 : enable bits 5:3 size of non-cacheable area #2 (within 128 mbytes) 000 : 64kb 001 : 128kb 010 : 256kb 011 : 512kb 100 : 1mb 101 : 2mb 110 : 4mb 111 : 8mb bits 2:0 a26 ~ a24 of non-cacheable area #2 (within 128 mbytes) register 5ah bits 7:0 a23 ~ a16 of non-cacheable area #2 (within 128 mbytes) register 5bh bit 7 fast gate a20 emulation enable 0 : disable 1 : enable the sequence to generate a20m# is: write d1h to i/o port 64h followed by i/o write to port 60h with data 00h. when this bit is enabled, the sis5501 responds the cycle by asserting devsel# in slowest timing. otherwise, the cycle is subtractively decoded by sis 5503, and then is passed to 8042 on the isa bus. bit 6 fast reset emulation enable
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 28 silicon integrated systems corporation 0 : disable 1 : enable the fast reset command is i/o write to port 64h with data 1111xxx0b. after the command is issued, the assertion of init or cpurst is delayed by 2us or 6us which can be programmed in bit 5, and is held for 25 cpuclk. bit 5 fast reset latency control 0 : 2us 1 : 6us bit 4 slow refresh enable (1:4) 0 : normal refresh 1 : slow refresh bit 3 dram write push to cas delay 0 : 2t 1 : 1t bit 2 de-turbo hold time 0 : hold 4 us 1 : hold 8 us (every 12 us) bit 1 de-turbo switch enable 0 : always turbo, ignore the status of de-turbo switch 1 : de-turbo switch enable bit 0 cas driving current control bit 0 ( please refer to reg. 5eh bit 0 for details) register 5ch bit 7 latency from ads# to monitor local memory status 0 : 3t 1 : 2t depending on the setting of this bit, the pci master bridge in the sis5501 may monitor the local memory status from the inside local memory decoder either by the end of t2 or t3. if the cpu initiates a pci cycle, it is determined to be converted to pci side from this point. specifically, brdy# is always returned to cpu one cpuclk later if the ctppb is not full, for post memory write cycles. thus, this bit also affects the cpu to pci post write speed. when it is set to 0, the post write rate is 5t for each double word. when it is set to 1, the rate is 4t per double word. for a qword pci memory write, the post write rate is 7t(bit7=1), or 8t(bit7=0).
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 29 silicon integrated systems corporation bit 6 enable refresh cycle when cpu is hold 0 : disable 1 : enable bit 5 enable snoop filter 0 : disable 1 : enable bit 4 cas# pulse width in pci master write cycle 0 : 1t 1 : 2t bit 3 latency from the disarming of "full" to the assertion of brdy# for the pending cpu to pci write cycle 0 : 1t 1 : 2t bit 2 selection of kwe# synchronization 0 : kwe# is synchronized with aclk (recommended) 1 : kwe# is synchronized with cpuclk bit 1 l2 tag length 0 : 8 bits 1 : 7 bits bit 0 memory parity enable/disable 0: enable parity error detection (default value) 1: disable parity error detection register 5dh pci control register bits 7:6 pci clock frequency selection 00 : pciclk=cpuclk/2 01 : pciclk=cpuclk/1.5 10 : reserved 11 : pciclk=14mhz bit 5 maximum burstable address range in pci master cycles 0 : 512 bytes 1 : 1 kbytes this bit defines the maximum bursting length for each frame# asserting.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 30 silicon integrated systems corporation bit 4 latency from reading l2/dram to the assertion of trdy# in pci master read cycles 0 : 1t 1 : 2t bit 3 latency from packing one qword into ptmpb to the assertion of cas#(or kwe#) 0 : 1t 1 : 2t this latency is reserved for the post write data propagating onto md bus, and also for the parity generation so that minimum set up time for md data to cas# will not be violated. bit 2 latency from trdy# to brdy# in cpu read/write pci slave cycles 0 : 2 cpuclks 1 : 3 cpuclks bit 1 cpu-to-pci burst memory write enable 0 : disable 1 : enable bit 0 cpu-to-pci post memory write enable 0 : disable 1 : enable register 5eh this register mainly defines the enable bits for the events monitored by system standby timer. if any monitored event occurs during the programmed time, the system standby timer will be reloaded and starts to count down again. bit 7 programmable 10-bit i/o port when set, any i/o access to the address will cause the timer be reloaded. the address is defined in registers 66h and 67h. bit 6 programmable 16-bit i/o port when set, any i/o access to the address will cause the timer be reloaded. the address is defined in registers 6dh and 6eh. bit 5 hard disk port when set, any i/o access to the hard disk ports ( 1f0-1f7h or 3f6h) will cause the timer be reloaded. bit 4 serial port
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 31 silicon integrated systems corporation when set, any i/o access to the serial ports ( 2f8-2ffh, 3f8-3ffh, 2e8-2efh or 3e8-3efh) will cause the timer be reloaded. bit 3 parallel port when set, any i/o access to the parallel ports ( 278-27fh, 378-37fh or 3bc- 3beh) will cause the timer be reloaded. bit 2 hold when set, any event from the isa master or the pci local master will cause the timer be reloaded. bit 1 irq1-15, nmi when set, any event from the irq1-15 or nmi will cause the timer be reloaded. bit 0 cas driving current control bit 1 register 5b bit 0 and 5e bit 0 are used to control cas driving current. register 5b bit 0 register 5e bit 0 minimum current 0 0 8ma (default) 1 0 4ma 0 1 12ma 1 1 8ma register 5fh bits 7:6 define the events monitored by the monitor standby timer bits 5:0 define the events to break the monitor and system standby state. bit 7 irq 1-15, nmi when set, any event from the irq1-15 or nmi will cause the monitor standby timer be reloaded. bit 6 hold when set, any event from the isa master or the pci local master will cause the monitor standby timer be reloaded. bit 5 irq 1-15, nmi when enabled, any event from the irq1-15 or nmi will bring the monitor back to the normal state from the standby state. bit 4 hold
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 32 silicon integrated systems corporation when enabled, any event from the isa master or the pci local master will bring the monitor back to the normal state from the standby state. bit 3 irq 1-15, nmi when enabled, any event from the irq1-15 or nmi will de-assert the stpclk#. bit 2 hold when enabled, any event from the isa master or the pci local master will de- assert the stpclk#. bit 1 init when enabled, an event from the init will de-assert the stpclk#. bit 0 reserved (must be '0') register 60h bit 7 reserved. it should be written with 0. bit 6 reserved. it should be written with 0. bit 5 stpclk# enable when set, writing a '1' to bit 3 of register 60h will cause the stpclk# to become active. this bit can be cleared. bit 4 throttling enable when set, writing a '1' to bit 3 of register 60h will cause the stpclk# throttling state to become active. the throttling function can be disabled by clearing this bit. bit 3 stpclk# control when this bit is set, the stpclk# will be asserted or the throttling function will be enabled depending on bits 5 and 4. if both bits 5 and 4 are enabled, the system will do the throttling function. bit 2 break sw., keyboard reset selection (pin 138) 0: kbrst # 1: break# the break sw. disable function can be done by programming register 68 bit 1 to "0". bit 1 apm smi when register 68h bit 0 is enabled, and a '1' is written to this bit, an smi is generated. it is used by the software controlled smi function like apm. this bit should be cleared at the end of the smi handler.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 33 silicon integrated systems corporation bit 0 reserved. register 61h stpclk# assertion timer bits 7:0 bits 7-0 define the period of the stpclk# assertion time when the stpclk# enable bit is set. the timer will not start to count until the stop grant special cycle is received. the timer slot is 35 us. register 62h stpclk# de-assertion timer bits 7:0 bits 7-0 define the period of the stpclk# de-assertion time when the stpclk# enable bit is set. the timer starts to count when the stpclk# assertion timer expires. when these two registers are read, the current values are returned. register 63h system standby timer bits 7:0 the register defines the duration of the system standby timer. when the system standby timer expires, the system enters system standby state. if any non-masked event occurs before the timer expires, the timer is reloaded with programmed number and the timer starts counting down again. register 64h smram mapping address. bits 7:0 correspond to host address a[27:20]. this register together with register 65h define smram location. smram location can either be set to a non-shadow, non-cacheable location by selecting e segment as defined in register 65h or be implemented through logical address remap scheme. logical address remap is done through comparing the upper 11 bits of access address with the address bits defined in register 64h and 65h. if addresses are compared equal and sram area selection has been set to either a or b segment, then access is remapped into an a or b segment access. the smram mapping address should be set up by bios during the post process and the smi service routine is also moved into the smram area during this process. when the system is in the smm mode or the smram access control bit is enabled, any access to smram area will be redirected as defined by these two registers. note: the smram mapping address defines 1mb granularity and the logical address must not set to the first 1mb memory area.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 34 silicon integrated systems corporation register 65h bits 7:5 smram area selection 000 : e0000h-e7fffh 100 : a0000h-a7fffh 010 : a0000h-affffh 110 : b0000h-b7fffh 001 : b0000h-bffffh others : reserved the smram area is non-cacheable, and non-shadowed. e0000h-e7fffh is a physical and logical address space. the other selections can be used to relocate the smram from the pre-defined area (as defined in registers 64h and 65h) during smm. bit 4 smram access control 1: when set, the smram area can be used. this bit can be set whenever it is necessary to access the smram area. it is cleared after the access is finished. 0: the smram area can only be accessed during the smi handler. bit 3 flush# (de-turbo mode), adsc# selection (pin 13) 0: adsc# 1: flush# (de-turbo mode) bits 2 : 0 bits 2-0 correspond to host address a[30:28]. register 66h bit 7 reserved (must be ' 0 ') bits 6:5 define the time slot of the monitor standby timer 00 : 6.6 seconds 01 : 0.84 seconds 10 : 13.3 milli-seconds 11 : 1.6 milli-seconds bits 4:2 programmable 10-bit i/o port address mask bits 000 : no mask 001 : a0 masked 010 : a1-a0 masked 011 : a2-a0 masked 100 : a3-a0 masked
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 35 silicon integrated systems corporation 101 : a4-a0 masked 110 : a5-a0 masked 111 : a6-a0 masked bits 1:0 programmable 10-bit i/o port address bits a1, a0. bits 1:0 correspond to the address bits a1 and a0. register 67h bits 7:0 bits 7:0 define the programmable 10-bit i/o port address bits a[9:2]. register 68h this register defines the enable status of the devices in smm. the bits 6:2 are set when the devices are in standby state and cleared when the respective devices are in normal state. bit 7 system standby smi enable when no non-masked event occurs during the programmed duration of the system standby timer, the timer expires. if this bit is enabled, the smi# is generated and the system enters the system standby state. bit 6 programmable 10-bit i/o port wake up smi enable when set, any i/o access to this port will be monitored to generate the smi# to wake up this i/o port from the standby state to the normal state. this bit is enabled only when the i/o port is in the standby state. bit 5 programmable 16-bit i/o port wake up smi enable when set, any i/o access to this port will be monitored to generate the smi# to wake up this i/o port from the standby state to the normal state. this bit is enabled only when the i/o port is in the standby state. bit 4 serial ports wake up smi enable when set, any i/o access to the serial ports will be monitored to generate the smi# to wake up the serial ports from the standby state to the normal state. this bit is enabled only when the serial ports are in the standby state. bit 3 parallel ports wake up smi enable when set, any i/o access to the parallel ports will be monitored to generate the smi# to wake up the parallel ports from the standby state to the normal state. this bit is enabled only when the parallel ports are in the standby state. bit 2 hard disk port smi enable
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 36 silicon integrated systems corporation when set, any i/o access to the hard disk port will be monitored to generate the smi# to wake up the hard disk from the standby state to the normal state. this bit is enabled only when the hard disk port is in the standby state. bit 1 break switch smi enable when set, the break switch can be pressed to generate the smi# for the system to enter the standby state. bit 0 software smi enable when set, an i/o write to register 60h bit 1 will generate an smi. register 69h this register defines the smi request status. if the respective smi enable bit is set, each specific event will cause the respective bit to be set. the asserted bit should be cleared at the end of the smi handler. bit 7 system standby smi request this bit is set when the system standby timer expires. bit 6 programmable 10-bit i/o port wake up request this bit is set when there is an i/o access to the port. bit 5 programmable 16-bit i/o port wake up request this bit is set when there is an i/o access to the port. bit 4 serial ports wake up request this bit is set when the serial ports are accessed. bit 3 parallel ports wake up request this bit is set when the parallel ports are accessed. bit 2 hard disk port wake up request this bit is set when the hard disk port is accessed. bit 1 break switch smi request this bit is set when the break switch is pressed. bit 0 software smi request this bit is set when an i/o write to the bit 1 of register 60h. register 6ah bit 7 monitor standby smi enable 0 : disable 1 : enable
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 37 silicon integrated systems corporation when there is no access from the irq1-15, hold and nmi during the programmed time of the monitor standby timer, the timer expires. if this bit is set, an smi is generated to bring the monitor to the standby state. bit 6 monitor standby smi request this bit is set when the monitor standby timer expires. this bit should be cleared at the end of the smi handler. bit 5 monitor wake up smi enable when set, any event from the irq1-15, hold or nmi will be monitored to generate the smi# to wake up the monitor from the standby state to the normal state. bit 4 monitor wake up request this bit is set when there is an event from the irq1-15, hold or nmi, and the monitor is in the standby state. bit 3 throttling wake up smi request this bit is set when there is any unmasked event from the nmi, init, irq1-15, or hold when the system is in the throttling state. bit 2 throttling wake up smi enable when set, any unmasked event from the nmi, init, irq1-15, or hold will cause an smi to be generated to bring the system back to the normal state from the throttling state. bit 1 system wake up smi enable when set, any unmasked event from the nmi, init, irq1-15, or hold will cause an smi to be generated to bring the system back to the normal state from the standby state. bit 0 system wake up smi request this bit is set when there is any unmasked event from the nmi, init, irq1-15, or hold when the system is in the standby state. register 6bh monitor standby timer - low byte bits 7:0 bits 7:0 define the low byte of the monitor standby timer. it is a count-down timer and the time slot is programmable for 6.6s, 0.84s, 13.3 ms or 1.6ms. the value programmed to this register is loaded when the timer is enabled and the timer starts counting down. the timer is reloaded when an event from the irq1-15, hold or nmi occurs before the timer expires. when this register is read, the current value is returned.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 38 silicon integrated systems corporation register 6ch monitor standby timer - high byte bits 7:0 bits 7:0 define the high byte of the monitor standby timer. register 6dh programmable 16-bit i/o port - low byte bits 7:0 bits 7:0 define the low byte of the programmable 16-bit i/o port. register 6eh programmable 16-bit i/o port - high byte bits 7:0 bits 7:0 define the high byte of the programmable 16-bit i/o port. register 6fh this register except bit 7 mainly defines the events monitored by the system standby timer. if any unmasked event occurs before the timer expires, the system standby timer will be reloaded and the timer starts to count down again. bit 7 return bus to cpu after sioreq# is serviced 0 : disable 1 : enable bit 6 smout it is reserved for the application circuit. bit 5 a0000h - a ffffh or b 0000 - b ffffh address trap when set, any memory access to the address range will cause the timer to be reloaded. bit 4 c0000h - c7 fffh address trap when set, any memory access to the address range will cause the timer to be reloaded. bit 3 3b0-3bfh, 3c0-3cfh, 3d0-3dfh address trap when set, any i/o access to the i/o addresses will cause the timer to be reloaded. bit 2 secondary drive port when set, any i/o access to the secondary drive port (170-17fh, 320-32fh, 3f7h) will reload the system standby timer. bits 1:0 system standby timer slot 11 : 8.85 milli seconds 10 : 70 milli seconds 01 : 1.1 seconds 00 : 9 seconds
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 39 silicon integrated systems corporation register 70h ~ 77h dram boundary each register records the accumulated dram size including the present and previous banks. bits 7:0 dram bank boundary address a[28:21] 00h: 0mbyte 01h: 2mbyte 02h: 4mbyte 04h: 8mbyte : note: please refer to "2.6 dram controller" for detailed information. register 78h bits 7:6 edo brdy# timing selection 00,10: no edo dram 01: brdy# type 1 timing (6-2-2-2) 11: brdy# type 2 timing (7-2-2-2) bits 5:4 edo mdle to 5502 timing selection 00,10: no edo dram 01: mdle type 1 timing (6-2-2-2) 11: mdle type 2 timing (7-2-2-2) bit 3 adsv#, ras6# selection (pin 12) 0: select adsv# 1: select ras6# bit 2 adsc#/flush#, ras7# selection (pin 13) 0: select adsc#/flush# 1: select ras7# bit 1 na#, ras4# selection (pin 193) 0: select na# 1: select ras4# bit 0 ma11, ras5# selection (pin 56) 0: select ma11 1: select ras5# note: the function of pin 12, pin 13, pin 56, and pin 193 can be chosen by register 78 bits 0~3 or hardware trap.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 40 silicon integrated systems corporation register 79h dram bank boundary address a29 bits 7:0 corresponds to a29 of bank 7~0 register 7ah bit 7 m1 smac access it must be set whenever the m1 ccr1 bit 2 is set and cleared if ccr1 bit 3 is cleared. bit 6 m1 mmac access if set, access to address within smm space is conducted to main memory instead of smm area. it must be set whenever the m1 ccr1 bit 3 is set and cleared if ccr1 bit 3 is cleared. in the m1's specification, the smiact will be de-asserted when mmac is set and re-asserted after it is cleared. this allows the smi service routine to access normal memory area instead of smm memory area. bit 5 m1 cpu it should be set if the current cpu is m1. bit 4 toggle mode enable 0: break sw. without toggle mode 1: break sw. with toggle mode bit 3 flush function block mode it is suggested to block the flush ( deturbo mode) when the stpclk is asserted. 0: un-block 1: block bit 2 reserved bit 1 control register 7dh 0: disable register 7dh. 1: enable register 7dh. when the bit 0 of register 5ch is set to zero, the parity checking function of 5501 is enabled. when register 5ch bit 0 and 7ah bit 1 are set to "1", the parity check of each bank is controlled by register 7dh. bit 0 reserved register 7bh bit 7 ad[31:0] output current selection
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 41 silicon integrated systems corporation 0: 50ma/2.2v (default value) 1: 95ma/2.2v bit 6 frame#, irdy#, trdy#, devsel#, c/be[3:0]# output current selection 0: 50ma/2.2v (default value) 1: 95ma/2.2v bit 5 gnt[3:0]#, par, serr# output current selection 0: 50ma/2.2v (default value) 1: 95ma/2.2v bits 4:0 reserved register 7ch bit 7 set cmpop synchronous to cas# 0: cmpop is active after cas# is active for 1t. 1: cmpop and cas# are active at the same time. bit 6 edo dram write cas# pulse width control bit 0: disable register 7ch bit 4. 1: enable register 7ch bit 4. bit 5 mdle control in edo write access 0: according to bits 5 and 4 of register 78h. 1: mdle and cas# are active at the same time. bit 4 edo dram write cas# pulse width 0: 1t 1: 2t in data sheet rev. 1.0, register 7ch bit 1 is used to set the cas# pulse width of edo dram read and write cycle. from 5501 rev. 1c, register 7ch bit 1 is only used to define the cas# pulse width in read cycle while bit 4 of register 7ch is used to define the cas# pulse width in write cycle. bit 3 set mdle always high this bit is only for testing purpose. 0: disable 1: enable bit 2 standard sram first cache read/write cycle setting 0: read 3t and write 3t
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 42 silicon integrated systems corporation 1: read 3t and write 4t in the original design, bits 7 and 6 of register 52h are used to define the first cycle time of cache burst read and write cycle when using standard sram. when bits 7 and 6 of register 52h are set to "10", the first cycle time is 3t for both read and write cycle. when bit 2 of register 7ch is set to "1", the first cycle time is redefined to 3t for read cycle and 4t for write cycle. this bit is only valid when the first cycle time is set to 3t defined in bit 7 and 6 oh register 52h. bit 1 access edo dram cas# pulse width 0: 2t 1: 1t bit 0 access edo dram cas# pre-charge time 0: 2t 1: 1t note: it is recommended that set the cas# pulse width and pre-charge time to 1t when the edo dram is used. register 7dh banks 7~0 parity disable control this register is valid when bit 1 of register 7a is set. bits 7:0 bank parity disable control bit 0: enable parity check. 1: disable parity check. register 7eh bit 7 setting bank 7 standard/edo type dram 0: standard dram 1: edo type dram bit 6 setting bank 6 standard/edo type dram 0: standard dram 1: edo type dram bit 5 setting bank 5 standard/edo type dram 0: standard dram 1: edo type dram bit 4 setting bank 4 standard/edo type dram 0: standard dram 1: edo type dram
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 43 silicon integrated systems corporation bit 3 setting bank 3 standard/edo type dram 0: standard dram 1: edo type dram bit 2 setting bank 2 standard/edo type dram 0: standard dram 1: edo type dram bit 1 setting bank 1 standard/edo type dram 0: standard dram 1: edo type dram bit 0 setting bank 0 standard/edo type dram 0: standard dram 1: edo type dram 2.11 pin assignment and description 2.11.1 hardware trap 5501 will strobe the status of gnt[3:0]# on the rising edge of pwrgd to determine the function of pin 12, 13, 56, and 193. the definition is described below: pin no. function condition 12 ras6# gnt2# pulled low via 10k ohms resistor 13 ras7# gnt3# pulled low via 10k ohms resistor 56 ras5# gnt1# pulled low via 10k ohms resistor 193 ras4# gnt0# pulled low via 10k ohms resistor 12 adsv# gnt2# pulled high via 10k ohms resistor 13 adsc#/flush# gnt3# pulled high via 10k ohms resistor 56 ma11 gnt1# pulled high via 10k ohms resistor 193 na# gnt0# pulled high via 10k ohms resistor due to pin restriction, pin 13 of 5501 is shared by adsc#, flush#, and ras7#. the hardware trap can only distinguish adsc#/flush# and ras7#. in order to distinguish adsc# and flush#, bit 3 of register 65h is implemented. the definition of register 65h bit 3 is described below: register 65h bit 3 "0" adsc# "1" flush# beside the hardware method, software method is also provided to define the multi-function pins. the following is the method to use hardware trap or register to define the multi-function pins.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 44 silicon integrated systems corporation by hardware trap: ? set bits[3:0] of register 78h to "0" ? select function through gnt[3:0]# by software: ? pull gnt[3:0]# to logic "high" ? select function through bits[3:0] of register 78h 2.11.2 pin assignment
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 45 silicon integrated systems corporation 104 100 95 90 85 80 75 70 65 60 55 53 208 205 200 195 190 185 180 175 170 165 160 157 ha4 ha6 ha7 ha8 ha10 ha5 ha11 ha9 ha12 ha13 ha14 ha15 ha16 ha17 ha18 ha19 ha20 cpurst hbe7# hbe6# hbe5# hbe4# hbe3# hbe1# hbe2# hbe0# vss a20m# w/r# hitm# eads# d/c# ads# cpuhlda smiact# cpuhold na#/ras4# brdy# vss ken# cache# m/io# vdd3 kce0#/cw e0# kce1/cw e2# kce2#/cw e2# kce3#/cw e3# vss kce4#/cw e4# kce5#/cw e5# kce6#/cw e6# kce7#/cw e7# 5501
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 46 silicon integrated systems corporation 2.11.3 pin listing ( # means active low) 1=cale 5v/3.3v 48=ma3 5v 95=ad20 5v 2=ka3/ka4y 5v/3.3v 49=ma4 5v 96=ad21 5v 3=ka4x 5v/3.3v 50=ma5 5v 97=ad22 5v 4=kwy1# 5v/3.3v 51=ma6 5v 98=ad23 5v 5=kwy0# 5v/3.3v 52=ma7 5v 99=ad24 5v 6=vss 53=ma8 5v 100=ad25 5v 7=kwx1# 5v/3.3v 54=ma9 5v 101=ad26 5v 8=kwx0# 5v/3.3v 55=ma10 5v 102=ad27 5v 9=krey#/coe1# 5v/3.3v 56=ma11/ras5# 5v 103=ad28 5v 10=krex#/coe0# 5v/3.3v 57=hgdw 5v 104=ad29 5v 11=vss 58=adle# 5v 105=ad30 5v 12=adsv#/ras6# 5v/3.3v 59=cppop 5v 106=ad31 5v 13=adsc#/flush #/ras7# 5v/3.3v 60=cppsh 5v 107=c/be0# 5v 14=vdd3 5v/3.3v 61=cmpop 5v 108=c/be1# 5v 15=ta0 5v 62=cmpsh 5v 109=vss 16=ta1 5v 63=mdle 5v 110=c/be2# 5v 17=ta2 5v 64=prdle 5v 111=c/be3# 5v 18=ta3 5v 65=adoe 5v 112=req0# 5v 19=ta4 5v 66=parity# 5v 113=req1# 5v 20=ta5 5v 67=hcr0 5v 114=req2# 5v 21=ta6 5v 68=vss 115=req3# 5v 22=ta7 5v 69=hcr1 5v 116=gnt0# 5v 23=altwe# 5v 70=hlda 5v 117=gnt1# 5v 24=alt 5v 71=pciclko 5v 118=gnt2# 5v 25=tagwe# 5v 72=ad0 5v 119=gnt3# 5v 26=cas0# 5v 73=ad1 5v 120=stop# 5v 27=cas1# 5v 74=ad2 5v 121=devsel# 5v 28=cas2# 5v 75=ad3 5v 122=trdy# 5v 29=cas3# 5v 76=ad4 5v 123=irdy# 5v 30=cpuclk 5v 77=ad5 5v 124=frame# 5v 31=vss 78=ad6 5v 125=plock# 5v 32=cas4# 5v 79=ad7 5v 126=par 5v 33=cas5# 5v 80=vdd 5v 127=serr# 5v 34=cas6# 5v 81=ad8 5v 128=vss 35=cas7# 5v 82=ad9 5v 129=pciclki 5v 36=aclk 5v 83=pwrgd 5v 130=siognt# 5v 37=vss 84=vss 131=sioreq# 5v 38=ras0# 5v 85=ad10 5v 132=pcirst# 5v 39=ras1# 5v 86=ad11 5v 133=smout 5v 40=vdd 5v 87=ad12 5v 134=wakeup1 5v 41=ras2# 5v 88=ad13 5v 135=wakeup0 5v 42=ras3# 5v 89=ad14 5v 136=vdd 5v 43=vss 90=ad15 5v 137=turbo 5v 44=ramw# 5v 91=ad16 5v 138=kbrst#/break# 5v 45=ma0 5v 92=ad17 5v 139=vss 46=ma1 5v 93=ad18 5v 140=osc 5v 47=ma2 5v 94=ad19 5v 141=vdd3 5v/3.3v
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 47 silicon integrated systems corporation 142=stpclk# 5v/3.3v 176=hbe6# 5v/3.3v 143=init 5v/3.3v 177=hbe5# 5v/3.3v 144=smi# 5v/3.3v 178=hbe4# 5v/3.3v 145=ha23 5v/3.3v 179=hbe3# 5v/3.3v 146=ha21 5v/3.3v 180=hbe2# 5v/3.3v 147=ha24 5v/3.3v 181=hbe1# 5v/3.3v 148=ha22 5v/3.3v 182=hbe0# 5v/3.3v 149=ha27 5v/3.3v 183=vss 150=ha26 5v/3.3v 184=a20m# 5v/3.3v 151=ha25 5v/3.3v 185=w/r# 5v/3.3v 152=ha28 5v/3.3v 186=hitm# 5v/3.3v 153=ha31 5v/3.3v 187=eads# 5v/3.3v 154=ha29 5v/3.3v 188=d/c# 5v/3.3v 155=ha30 5v/3.3v 189=ads# 5v/3.3v 156=ha3 5v/3.3v 190=cpuhlda 5v/3.3v 157=ha4 5v/3.3v 191=smiact# 5v/3.3v 158=ha6 5v/3.3v 192=cpuhold 5v/3.3v 159=ha7 5v/3.3v 193=na#/ras4# 5v/3.3v 160=ha8 5v/3.3v 194=brdy# 5v/3.3v 161=ha10 5v/3.3v 195=vss 162=ha5 5v/3.3v 196=ken# 5v/3.3v 163=ha11 5v/3.3v 197=cache# 5v/3.3v 164=ha9 5v/3.3v 198=m/io# 5v/3.3v 165=ha12 5v/3.3v 199=vdd3 5v/3.3v 166=ha13 5v/3.3v 200=kce0#/cwe0# 5v/3.3v 167=ha14 5v/3.3v 201=kce1#/cwe1# 5v/3.3v 168=ha15 5v/3.3v 202=kce2#/cwe2# 5v/3.3v 169=ha16 5v/3.3v 203=kce3#/cwe3# 5v/3.3v 170=ha17 5v/3.3v 204=vss 171=ha18 5v/3.3v 205=kce4#/cwe4# 5v/3.3v 172=ha19 5v/3.3v 206=kce5#/cwe5# 5v/3.3v 173=ha20 5v/3.3v 207=kce6#/cwe6# 5v/3.3v 174=cpurst 5v/3.3v 208=kce7#/cwe7# 5v/3.3v 175=hbe7# 5v/3.3v
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 48 silicon integrated systems corporation 2.11.4 pin description host interface pin no. symbol type function 145-173 ha[31:3] i/o the cpu address is driven by the cpu during cpu bus cycles. the 5501 forwards it to either the dram or the pci bus depending on the address range. the address bus is driven by the 5501 during bus master cycles. 175-182 hbe[7:0]# i cpu byte enables indicate which byte lanes on the cpu data bus carry valid data during the current bus cycle. hbe7# indicates that the most significant byte of the data bus is valid while hbe0# indicates that the least significant byte of the data bus is valid. 189 ads# i address status is driven by the cpu to indicate the start of a cpu bus cycle. 198 m/io# i memory i/o definition is an input to indicate an i/o cycle when low, or a memory cycle when high. 185 w/r# i/o write/read from the cpu indicates whether the current cycle is a write or read access. it is an output during the pci master cycles. 188 d/c# i data/code is used to indicate whether the current cycle is a data or code access. 194 brdy# o burst ready indicates that data presented are valid during a burst cycle. 192 cpuhold o cpu hold request is used to request the control of the cpu bus. cpuhlda will be asserted by the cpu after completing the current bus cycle. 190 cpuhlda i cpu hold acknowledge comes from the cpu in response to a cpuhold request. it is active high and remains driven during bus hold period. cpuhlda indicates that the cpu has given the bus to another bus master. 186 hitm# i hit modified indicates the snoop cycle hits a modified line in the l1 cache of the cpu. 184 a20m# o a20 mask is the fast a20gate output to the cpu. it remains high during power up and cpu reset period. it forces a20 to go low when active.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 49 silicon integrated systems corporation 196 ken# o the cpu cache enable pin is used when the current cycle is cacheable to the l1 cache of the cpu. it is an active low signal asserted by the 5501 during cacheable cycles. 197 cache# i the cache pin indicates an internally cacheable read cycle or a burst write-back cycle. if this pin is driven inactive during a read cycle, the cpu will not cache the returned data, regardless of the state of the ken# pin. 187 eads# o the eads# is driven to indicate that a valid external address has been driven to the cpu address pins to be used for an inquire cycle. 174 cpurst o reset cpu is an active high output to reset the cpu. 143 init o the initialization output forces the cpu to begin execution in a known state. the cpu state after init is the same as the state after cpurst except that the internal caches, model specific registers, and floating point registers retain the values they had prior to init. 144 smi# o system management interrupt is used to indicate the occurrence of system management events. it is connected directly to the cpu smi# input. 191 smiact# i the smiact# pin is used as the smi acknowledgment input from the cpu to indicate that the smi is being acknowledged and the processor is operating in system management mode(smm). 142 stpclk# o stop clock indicates a stop clock request to the cpu.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 50 silicon integrated systems corporation cache & dram interface pin no. symbol type function 22-15 ta[7:0] i/o tag ram data bus lines. 24 alt i/o the alt bit indicates the particular line in the 2nd level cache contains modified data. 3 ka4x o cache address bit 4 for even bank in an interleaved cache configuration.. 2 ka3/ka4y o cache address bit 4 for odd bank, or cache address bit 3 in non-interleaved mode. 10 krex#/coe0# o cache read enable for even bank of standard sram, or cache output enable for burst sram. 9 krey#/coe1# o cache read enable for odd bank of standard sram, or cache output enable for burst sram. when used as coe1#, it is a copy of coe0# for loading consideration. 8,7 kwx0/1# o cache write enable for standard sram, even bank. 5,4 kwy0/1# o cache write enable for standard sram, odd bank. 23 altwe# o the altwe# is the write strobe to the alt ram. this signal is active low when cache read miss or cache write hit occurs. it is used to update the alt bit. 25 tagwe# o tag ram write enable output. 208-205 203-200 kce[7:0]# / cwe[7:0]# o cache enable pins for standard sram indicate that the corresponding byte is accessed. cache write enable pins for burst sram to allow cache data ram update on a byte-by-byte basis. 1 cale o the cale controls the external latch between the host address lines and the cache address lines. when high, it allows the cpu address lines to propagate through external latches and onto cache address lines. when low, it is used to latch cache address lines. 42,41 39,38 ras[3:0]# o the ras[3:0]# are used to latch the row address on the ma bus. each ras[3:0]# corresponds to one dram row.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 51 silicon integrated systems corporation 35-32 29-26 cas[7:0]# o the cas[7:0]# are used to latch the column address on the ma bus. each cas[7:0]# corresponds to one byte of the eight-byte wide array. 44 ramw# o ram write is an active low output signal to enable local dram writes. 55-45 ma[10:0] o the ma[10:0] provide the row and column address to the dram. pci interface pin no. symbol type function 111,110 108,107 c/be[3:0]# i/o pci bus command and byte enables define the pci command during the address phase of a pci cycle, and the pci byte enables during the data phases. c/be[3:0]# are outputs when the 5501 is a pci bus master and inputs when it is a pci slave. 106-85 82,81 79-72 ad[31:0] i/o pci address /data bus in address phase: 1. when the 5501 is a pci bus master, ad[31:0] are output signals. 2. when the 5501 is a pci target, ad[31:0] are input signals. in data phase: 1. when the 5501 is a bus master of a memory read/write cycle, ad[31:0] are floating. 2. when the 5501 is a bus master of a configuration or an i/o cycle, ad[31:0] are input signals in a read cycle, and output signals in a write cycle. 3. when the 5501 is a target of a memory read/write cycle, ad[31:0] are floating. 4. when the 5501 is a target of a configuration or an i/o cycle, ad[31:0] are output signals in a read cycle, and input signals in a write cycle. 124 frame# i/o frame# is an output when the 5501 is a pci bus master. the 5501 drives frame# to indicate the beginning and duration of an access. when the 5501 is a pci slave, frame# is an input signal.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 52 silicon integrated systems corporation 123 irdy# i/o irdy# is an output when the 5501 is a pci bus master. the assertion of irdy# indicates the current pci bus master's ability to complete the current data phase of the transaction. for a read cycle, irdy# indicates that the pci bus master is prepared to accept the read data on the following rising edge of the pci clock. for a write cycle, irdy# indicates that the bus master has driven valid data on the pci bus. when the 5501 is a pci slave, irdy# is an input. 122 trdy# i/o trdy# is an output when the 5501 is a pci slave. the assertion of trdy# indicates the target agent's ability to complete the current data phase of the transaction. for a read cycle, trdy# indicates that the target has driven valid data onto the pci bus. for a write cycle, trdy# indicates that the target is prepared to accept data from the pci bus. when the 5501 is a pci master, it is an input. 121 devsel# i/o the 5501 drives devsel# based on the dram address range being accessed by a pci bus master or if the current configuration cycle is to the 5501. as an input it indicates if any device has responded to current pci bus cycle initiated by the 5501. 120 stop# i/o stop# indicates that the bus master must start terminating its current pci bus cycle at the next clock edge and release control of the pci bus. stop# is used for disconnect, retry, and target- abort sequences on the pci bus. 126 par o parity is an even parity generated across ad[31:0] and c/be[3:0]#. 127 serr# o system error is an open drain output for reporting errors. 115-112 req[3:0]# i pci bus request is used to indicate to the pci bus arbiter that an agent requires use of the pci bus. 119-116 gnt[3:0]# o pci bus grant indicates to an agent that access to the pci bus has been granted.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 53 silicon integrated systems corporation 125 plock# i pci lock indicates an exclusive bus operation that may require multiple transactions to complete. when plock# is sampled asserted at the beginning of a pci cycle, the 5501 considers itself a locked resource and remains in the locked state until plock# is sampled negated on a new pci cycle. 71 pciclko o the pciclko provides the clock for the 5501/5502/5503 and pci devices of the system. 129 pciclki i the pciclki input provides the fundamental timing and the internal operating frequency for the 5501. it runs at the same frequency and skew of the pci local bus. it should be generated from the pciclko signal through a clock distribution buffer. 132 pcirst# o the pci reset forces the pci devices to a known state. data buffer control interface pin no. symbol type function 69,67 hcr[1:0] o host data bus controls. these signals are driven by the 5501 and are used to control the 5502 hd[63:0] bus. they are defined as: 00: 5502 floats hd bus 01: 5502 drives ffffffff to hd bus 10: 5502 drives data from ad bus to hd bus 11: 5502 drives data from md bus to hd bus 58 adle# o ad bus data latch enable. this signal has the following functions: 1. latch hd or md data into the pci read buffer (prmb) 2. latch ad data into cpu read pci buffer on the rising edge of pciclki. 3. latch ad data into pci posted write buffer (ptmpb) on the rising edge of pciclki. 65 adoe o ad bus output enable. this signal is used to enable the 5502 to drive pci ad bus. it is asserted in cpu writes pci or pci master reads local memory cycles. 63 mdle o memory data read latch enable. this signal latches the data on the md bus when negated.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 54 silicon integrated systems corporation 60 cppsh o push cpu to pci posted write data into the 5502. the data on the hd bus is latched into the 5502 cpu to pci posted write buffer on cppsh rising edge. the edge also increases the write pointer to the next available loading entry in the buffer. 59 cppop o on the rising edge of cppop, the read pointer is changed to address the next available reading location. 62 cmpsh o when this signal is asserted, the data on the hd bus is written into the cpu to memory posted write buffer (ctmpb) on the rising edge of cpuclk, and the write pointer is also changed to address the next available location. 61 cmpop o pop cpu to memory posted write buffer data. when this signal is asserted, the read pointer of the cpu to memory posted write buffer is increased on the rising edge of cpuclk. 64 prdle o this signal latches the current output entry in the cpu to pci posted write buffer into the prelatch in the 5502. the output of the prelatch is driven onto the pci ad bus. in a pci master cycle, prdle is asserted when pci master is reading data from the secondary cache, or when pci master is writing data to the local memory. 57 hgdw o high double word indicator. the signal is driven high when: (1) a high dw from the hd bus is written into cpu to pci posted write buffer, (2) the cpu reads a high dw from pci bus, (3) pci master writes a high dw to local memory, (4) pci master reads a high dw from local memory. 66 parity# i parity bit, from the 5502.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 55 silicon integrated systems corporation multi-function pins pin no. symbol type function 193 na#/ras4# o this pin that can be used as na# or ras4# depends on the bios programming or hardware trap selection. next address is driven for one clock to the cpu to indicate that the memory system is ready to accept a new bus cycle. although the data transfer for the current cycle has not yet completed, the cpu may drive a internally pending cycle out to the address bus two clocks after na# is asserted. the ras4# are used to latch the row address on the ma bus. 56 ma11/ras5# o this pin that can be used as ma11 or ras5# depends on the bios programming or hardware trap selection. the ma11 provides the row and column address to the dram. the ras5# are used to latch the row address on the ma bus. 12 adsv#/ras6# o this pin that can be used as adsv# or ras6# depends on the bios programming or hardware trap selection. cache advance is driven to burst sram to advance the internal two-bit address counter to the next address of burst sequence. the ras6# are used to latch the row address on the ma bus. 13 adsc#/flush# /ras7# o this pin that can be used as adsc#, flush#, or ras7# depends on the bios programming or hardware trap selection. cache address strobe control causes the burst sram to latch the cache address. flush# is asserted during deturbo mode. it is used to force cpu to writeback all modified lines in the data cache and invalidate cpu internal cache. the ras7# are used to latch the row address on the ma bus.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 56 silicon integrated systems corporation others pin no. symbol type function 70 hlda o hold acknowledge. 133 smout o system management output control pin. it is used to control peripheral's power, clock...etc. 131 sioreq# i sio request from the 5503 to request the pci bus. 130 siognt# o sio grant. when asserted, siognt# indicates that the pci arbiter has granted use of the bus to the 5503. 138 kbrst#/brea k# i when the break switch enable bit is set, the kbrst# will be disabled. a signal from the break switch will cause the system enters the standby state. the pulse width of the break# must greater than 4 cpuclk. 137 turbo i turbo input pin. the system is in de-turbo mode when this pin is low. 134 wakeup1 i when this input is activated, the 5501 will reload the system standby timer. if it is inactive and the system standby timer expires, the system will enter system standby state. during the system standby state, if this input becomes active, the system will wake up from standby state and return back to normal state. 135 wakeup0 i when this input is activated, the 5501 will reload the monitor standby timer. if it is inactive and the monitor standby timer expires, the system will enter monitor standby state. during the monitor standby state, if this input becomes active, the system will wake up from standby state and return back to normal state. 140 osc i osc is a clock input for the timer and the dma controller. it is 14.318mhz and is generated by an external oscillator. 36 aclk i advanced cpu clock should lead the cpuclk by 3 to 7 ns to provide the clock for the 5501 internal cache control logic. 30 cpuclk i cpu clock input runs at the frequency and skew equal to those of the cpu clock. 83 pwrgd i power good is a power on reset and push button reset input. 40,80,136 vdd +5v dc power 14,141 199 vdd3 +3.3v dc power in 3v system +5v dc power in 5v system
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 57 silicon integrated systems corporation 6,11,31,37 43,68,84 109,128 139,183 195,204 vss ground 2.12 timing diagram cache burst read hit cycle 3-1-1-1 501cbr1 cpuclk ads# brdy# ka4x ka4y krex# krey# cache burst read hit cycle 4-2-2-2 501cbr2 cpuclk ads# brdy# ka4x ka4y krex# krey# cache burst read hit cycle 5-3-3-3 501cbr3 cpuclk ads# brdy# ka4x ka4y krex# krey#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 58 silicon integrated systems corporation cache burst write hit cycle 3-1-1-1 501cbw1 cpuclk ads# brdy# ka4x ka4y kwex# kwey# cache burst write hit cycle 4-2-2-2 501cbw2 cpuclk ads# brdy# ka4x ka4y kwex# kwey# cache burst write hit cycle 5-3-3-3 501cbw3 cpuclk ads# brdy# ka4x ka4y kwex# kwey#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 59 silicon integrated systems corporation cache miss update cycle only (wt or wb , dirty=0, dram:7-4-4-4 ) 5501cmu1 cpuclk ads# cas# ras# brdy# na# ma[11:0] cale kwex# kwey# ka4x ka4y cache miss update cycle only (wt or wb , dirty=0, dram:6-3-3-3 ) 5501cmu2 cpuclk ads# cas# ras# brdy# na# ma[11:0] cale kwex# kwey# ka4x ka4y
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 60 silicon integrated systems corporation cache miss,concurrent write back cycle ( cache:4-2-2-2 & dram:7-4-4-4 ) 5501cmwb cpuclk ads# cas# ras# brdy# cmpsh na# ma[11:0] cmpop cale kwex# kwey# ka4x ka4y ramw# krex# krey#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 61 silicon integrated systems corporation dram burst read - row miss 10-3-3-3 (cache 3/4-x-x-x) 5501dbr1 cpuclk ads# cas# ras# brdy# mdle na# ma[11:0] cale kwex# ka3 ka4x dram burst read - row miss 11-4-4-4 (cache 3/4-x-x-x) 5501dbr2 cpuclk ads# cas# ras# brdy# mdle na# ma[11:0] cale kwex# ka3 ka4x
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 62 silicon integrated systems corporation dram burst read - row miss 9-3-3-3 (cache 3/4-x-x-x) 5501dbr3 cpuclk ads# cas# ras# brdy# mdle na# ma[11:0] cale kwex# ka3 ka4x dram burst read - row miss 10-4-4-4 (cache 3/4-x-x-x) 5501dbr4 cpuclk ads# cas# ras# brdy# mdle na# ma[11:0] cale kwex# ka3 ka4x
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 63 silicon integrated systems corporation dram posted write - 4-2-2-2 , l2 cache write-through 5501dbw1 cpuclk ads# cas# ras# brdy# cmpsh ma[11:0] cmpop kwex# ka3 ka4x edo burst read (7-2-2-2) cpuclk ads# cas# ma cas# ma mdle brdy# ras# logic timing physical timing assume cas delay 10 ns ma delay 15 ns
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 64 silicon integrated systems corporation cpuclk ads# cas# edo burst write (posted write 4-2-2-2) brdy# cmpop ma cas# ma logic timing physical timing assume cas delay 10ns ma delay 15 ns 0cf8 0cfc f0 cf 5501 configuration register read cycle cpuclk ha[31:3] hbe[7:0]# ads# brdy# hgdw pciclk frame# irdy# devsel# trdy# prdle adoe adle#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 65 silicon integrated systems corporation 0cf8 0cfc f0 cf 501crw 5501 configuration register write cycle cpuclk ha[31:3] hbe[7:0]# ads# brdy# hgdw pciclk frame# irdy# devsel# trdy# prdle adoe adle# cpu read pci slave read low dw read high dw addr. addr. data 66 0 6 0 02 0 data 501crp cpuclk ha[31:3] hbe[7:0]# ads# brdy# hgdw pciclk ad[31:0] c/be[3:0]# frame# irdy# devsel# trdy# prdle adle# hcr[1:0]
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 66 silicon integrated systems corporation xxxxx800 xxxxx808 f0 0f 00 xxx800 data 0 cpu to pci psoted write cycle 7 1 wait state 501ctpp cpuclk ha[31:3] hbe[7:0]# ads# brdy# hgdw pciclk ad[31:0] c/be[3:0]# frame# irdy# devsel# trdy# adoe cppsh cppop prdle pci master reads a high dw from l2,na=sal 501prl2 pciclk frame# irdy# devsel# kre# trdy# hgdw adoe adle#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 67 silicon integrated systems corporation pci master writes a qw to l2/dram, na=sal, page hit 00 10 00 501prl2d cpuclk pciclk frame# irdy# devsel# eads# kwe#/cas# trdy# hgdw hcr[1:0] adle# cale prdle ramw#
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 68 silicon integrated systems corporation snoop hit a modified line in l1, l2 miss pci master writes the last two qw in the 16 line boundary, disconnect row address 1st qw column addr 2nd qw 3rd qw 4th qw 3rd qw 4th qw 501snp2 cpuclk pciclk frame# irdy# devsel# trdy# stop# eads# hitm# cpuhold cpuhlda ads# brdy# ras# cas# ma ramw# prdle adle# hgdw cale
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 69 silicon integrated systems corporation 00100000 cpu drive 00100000 00100000 00100008 00100010 00100018 snoop hit a modified line in l1, hit l2, pci master read one line from l2 501snp1 cpuclk pciclk frame# irdy# devsel# trdy# eads# hitm# cpuhold cpuhlda ha[31:3] ads# brdy# kwe# kre# adoe prdle adle# hgdw
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 70 silicon integrated systems corporation 2.13 electrical characteristics 2.13.1 absolute maximum ratings parameter min max unit ambient operating temperature 0 70 o c storage temperature -40 125 o c input voltage -0.3 5.5 v output voltage -0.5 5.5 v power dissipation 1 w note: stress above these listed may cause permanent damage to device. functional operation of this device should be restricted to the conditions described under operating conditions. 2.13.2 dc characteristics ta = 0 - 70 o c, vss = 0v , vdd=5v+5%, vdd3=3.3v+ 5% symbol parameter min max unit condition v il 1 input low voltage -0.3 0.8 v note 1 , vdd3=3.3v v ih1 input high voltage 2.2 vdd3+0.3v v note 1 v il2 input low voltage -0.3 0.8 v note 2 v ih2 input high voltage 2.2 vdd+0.3 v note 2 v t1- schmitt trigger threshold voltage falling edge 1.6 v note 3 v t1+ schmitt trigger threshold voltage rising edge 3.2 v note 3 v h1 hysteresis voltage 0.3 1.2 v note 3 v ol1 output low voltage 0.45 v note 4 v oh1 output high voltage 2.4 v note 4 v ol2 output low voltage 0.4 v note 5 v oh2 output high voltage 2.0 vdd3 v note 5 i ol1 output low current 4 ma note 6 i oh1 output high current 4 ma note 6 i ol2 output low current 6 ma note 7 i oh2 output high current 6 ma note 7 i ol3 output low current 8 ma note 8 i oh3 output high current 8 ma note 8 i ol4 output low current 16 ma note 9 i oh4 output high current 16 ma note 9 i ol5 output low current 4 ma note 10 i oh5 output high current 1 ma note 10 , note 11 i ih input leakage current +10 ma
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 71 silicon integrated systems corporation i il input leakage current -10 ma c in input capacitance 12 pf fc=1 mhz c out output capacitance 12 pf fc=1 mhz c i/o i/o capacitance 12 pf fc=1 mhz i cc3 power supply current of vdd3 40 ma 3.3v, 66mhz note: 1. v il1 and v ih1 are applicable to ha[31:3], w/r#, hbe[7:0]#, hitm#, d/c#, ads#, cpuhlda, smiact#, cache#, m/io# 2. v il2 and v ih2 are applicable to ta[7:0], alt, cpuclk, aclk, parity#, ad[31:0], c/be[3:0]#, req[3:0]#, stop#, devsel#, trdy#, irdy#, frame#, lock#, pciclki, siognt#, sioreq#, wakeup[1:0], turbo, kbrst#, osc 3. v t1- ,v t1+ and v h1 are applicable to pwrgd 4. v ol1 and v oh1 are applicable to ta[7:0], altwe#, alt, tagwe#, cas[7:0]#, ras[3:0]#, ramw#, ma11/ras5#, ma[10:0], hgdw, adle#, cppop, cppsh, cmpop, cmpsh, mdle, prdle, adoe, hcr[1:0], hlda, pciclko, ad[31:0], gnt[3:0]#, stop#, devsel#, trdy#, frame#, par, serr#, pcirst#, smout 5. v ol2 and v oh2 are applicable to cale, ka4y, ka4x, kwy[1:0]#, kwx[1:0]#, krex#, krey#, adsc#/flush#/ras7#, adsv#/ras6#, stpclk#, init, smi#, ha[31:3], cpurst, w/r#, a20m#, eads#, cpuhold, na#/ras4#, brdy#, ken#, kce[7:0]# 6. i ol1 and i oh1 are applicable to ta[7:0], altwe#, alt, tagwe#, ramw#, ma11/ras5#, ma[10:0], hgdw, adle#, cppop, cppsh, cmpop, cmpsh, mdle, prdle, adoe, hcr[1:0], hlda, pciclko, ad[31:0], c/be[3:0]#, gnt[3:0]#, par, serr#, pcirst#, smout, wakeup[1:0] 7. i ol2 and i oh2 are applicable to frame#, irdy#, trdy#, devsel#, stop#. 8. i ol3 and i oh3 are applicable to cas[7:0]# 9. i ol4 and i oh4 are applicable to ka4x, ka4y, kwy[1:0]#, kwx[1:0]#, adsv#/ras6#, adsc#/flush#/ras7#, ras[3:0]# 10. i ol5 and i oh5 are applicable to cale, krey#, krex#, stpclk#, init, smi#, ha[31:3], w/r#, eads#, cpuhold, na#/ras4#, brdy#, ken#, kce[7:0]#, cpurst, a20m# 11. i oh5 is 1ma in 3.3 system, when in 5v system, the i oh5 is 4ma. 12. the driving current of cas# and some pci bus signals are programmable. please refer to register description.
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 72 silicon integrated systems corporation 2.13.3 ac characteristics symbol parameter typ max unit cl t1 brdy# active delay from cpuclk 8 12 ns 35pf t2 brdy# inactive delay from cpuclk 6 9 ns 35pf t3 ken# active delay from cpuclk 7 11 ns 35pf t4 ken# inactive delay from cpuclk 5 8 ns 35pf t5 na# active delay from cpuclk 8 12 ns 35pf t6 na# inactive delay from cpuclk 6 9 ns 35pf t7 eads# active delay from cpuclk 8 12 ns 35pf t8 eads# inactive delay from cpuclk 6 9 ns 35pf t9 cpuhold active delay from cpuclk 8 12 ns 35pf t10 cpuhold inactive delay from cpuclk 6 9 ns 35pf t11 cpurst inactive delay from cpuclk 7 11 ns 35pf t12 cpurst high pulse width 25 cpuclk 35pf t13 krex#,krey# active delay from aclk 9 13 ns 100pf t14 krex#,krey# inactive delay from aclk 6 9 ns 100pf t15 kwx[0:1]#,kwy[0:1]# active delay from aclk 8 12 ns 100pf t16 kwx[0:1]#,kwy[0:1]# inactive delay from aclk 6 9 ns 100pf t17 kwx[0:1]#,kwy[0:1]# active delay from cpuclk 8 12 ns 100pf t18 kwx[0:1]#,kwy[0:1]# inactive delay from cpuclk 6 9 ns 100pf t19 kce[7:0]# active delay from ads# falling edge 7 12 ns 35pf t20 kce[7:0]# inactive delay from cpuclk 7 12 ns 35pf t21 mdle high active delay from cpuclk 5 8 ns 35pf t22 mdle high inactive delay from cpuclk 7 11 ns 35pf t23 ka4x,ka4y low valid delay from aclk 7 11 ns 100pf t24 ka4x,ka4y high valid delay from aclk 6 9 ns 100pf t25 ka4x,ka4y low valid delay from cpuclk in update cycle & write cycle 7 11 ns 100pf t26 ka4x,ka4y high valid delay from cpuclk in update cycle & write cycle 6 9 ns 100pf t27 tag output valid delay from cpuclk in update cycle 14 23 ns 35pf t28 ras[7:0]# active delay from cpuclk 12 18 ns 250pf t29 ras[7:0]# inactive delay from cpuclk 9 14 ns 250pf t30 cas[7:0]# active delay from cpuclk 11 16 ns 120pf t31 cas[7:0]# inactive delay from cpuclk 8 12 ns 120pf t32 ma[11:0] low valid delay from cpuclk 12 18 ns 35pf t33 ma[11:0] high valid delay from cpuclk 11 16 ns 35pf t34 ma[11:0] propagation delay from a[27:3] 8 12 ns 35pf t35 alt output valid delay from cpuclk 10 15 ns 35pf t36 altwe#,tagwe# active delay from cpuclk 9 14 ns 35pf t37 altwe#,tagwe# inactive delay from cpuclk 9 14 ns 35pf t38 a20m# active delay from cpuclk 9 14 ns 35pf t39 a20m# inactive delay from cpuclk 8 12 ns 35pf t40 ad[31:0],c/be[3:0]# output valid delay from pciclki 10 15 ns 50pf t41 prdle active delay from pciclki 9 14 ns 35pf t42 devsel#,frame#,irdy#,stop#,trdy# active delay from pciclki 10 15 ns 50pf t43 devsel#,frame#,irdy#,stop#,trdy# inactive delay from pciclki 9 14 ns 50pf
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 73 silicon integrated systems corporation t44 gnt[3:0]#,par,serr#,siognt#,stpclk# active delay from pciclki 10 15 ns 50pf t45 gnt[3:0]#,par,serr#,siognt#,stpclk# inactive delay from pciclki 10 15 ns 50pf t46 ha[31:3] drive output valid delay from pciclki 12 18 ns 50pf t47 hcr[1:0],hgdw active delay from cpuclk 7 11 ns 35pf t48 hlda active delay from cpuclk 8 12 ns 35pf t49 hlda inactive delay from cpuclk 7 11 ns 35pf t50 init# active delay from cpuclk 7 11 ns 35pf t51 init# inactive delay from cpuclk 6 9 ns 35pf t52 mdle active delay from cpuclk 7 11 ns 35pf t53 mdle inactive delay from cpuclk 6 9 ns 35pf t54 pciclko,pcirst active delay from cpuclk 8 12 ns 50pf t55 ramw# active delay from cpuclk 11 16 ns 35pf t56 ramw# inactive delay from cpuclk 8 12 ns 35pf t57 smout active delay from cpuclk 10 15 ns 50pf t58 adsc# active delay from cpuclk 7 11 ns 90pf t59 adsc# inactive delay from cpuclk 6 9 ns 90pf t60 adsv# active delay from cpuclk 7 11 ns 150pf t61 adsv# inactive delay from cpuclk 6 9 ns 150pf t62 cppsh active delay from cpuclk 4 6 ns 35pf t63 cppop active delay from pciclk 8 12 ns 35pf t64 cppsh inactive delay from cpuclk 7 11 ns 35pf t65 cppop inactive delay from pciclk 10 15 ns 35pf t66 adoe active delay from pciclk 6 9 ns 35pf t67 adoe inactive delay from pciclk 6 9 ns 35pf t68 adle# active delay from pciclk 6 9 ns 35pf t69 adle# inactive delay from pciclk 6 9 ns 35pf t70 pciclko high time (divided by 2) 15.2 ns 50pf t71 pciclko low time (divided by 2) 12.6 ns 50pf t72 pciclko high time (divided by 1.5) 12.5 ns 50pf t73 pciclko low time (divided by 1.5) 15.8 ns 50pf t74 pciclko rise time (divided by 2) 1.16 ns 50pf t75 pciclko fall time (divided by 2) 0.66 ns 50pf t76 pciclko rise time (divided by 1.5) 1.06 ns 50pf t77 pciclko fall time (divided by 1.5) 0.9 ns 50pf t78 hcr[1:0] fall time to cpuclk rising 4.5 ns 35pf t79 hcr[1:0] rise time to cpuclk rising 3.7 ns 35pf t80 cale# active delay from cpuclk 8 12 ns 35pf t81 cale# inactive delay from cpuclk 6 9 ns 35pf t82 smi# rise time to cpuclk rising 7.8 10 ns 35pf t83 smi# fall time to cpuclk rising 7.8 10 ns 35pf
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 74 silicon integrated systems corporation tr1 tf1 cpuclk signal1 tf1 = t1, t3, t5, t7, t10, t11, t17, t22, t23, t25, t27, t28, t30, t32, t36, t38, t49, t50, t53, t55, t58, t60, t64, t78, t80, t83 tr1 = t2, t4, t6, t8, t9, t18, t20, t21, t24, t26, t27, t29, t31, t33, t35, t37, t39, t47, t48, t51, t52, t54, t56, t57, t59, t61, t62, t79, t81, t82 signal1 = brdy#, ken#, na#, eads#, cpuhold, cpurst, kwx[0:1]#, kwy[0:1]#, kce[7:0]#, mdle, cale, ka4x, ka4y, ta[7:0], ras[7:0]#, cas[7:0]#, ma[11:0], alt, altwe#, tagwe#, a20m#, hlda, init#, pciclko, pcirst, ramw#, smout, adsc#, adsv#, gnt[3:0]#, par, serr#, siognt#, stpclk#, cppsh tr2 tf2 aclk signal2 tf2 = t13, t15, t23 tr2 = t14, t16, t24 signal2 = krex#, krey#, kwx[0:1]#, kwy[0:1]#, ka4x, ka4y tr3 tf3 pciclki signal3 tf3 = t40, t41,t42, t46, t44, t65, t67, t68 tr3 = t40, t41, t43, t46, t45, t63, t66, t69 signal3 = ad[31:0], c/be[3:0], adle#, adoe, prdle, devsel#, frame#, irdy#,stop#, trdy#, ha[31:3], cppop, adoe, adle
sis5501 pci/isa cache memory controller preliminary v2.0 april 2, 1995 75 silicon integrated systems corporation t19 t12 t12 t34 ads# kce[7:0]# cpurst ha[27:3] ma[11:0] pciclko tl4 th4 tr4 tf4 th4 = t70,t72 tl4 = t71, t73 tr4 = t74, t76 tf4 = t75, t77
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 76 silicon integrated systems corporation 3 SIS5502 3.1 features ? ? ? ? supports the full 64-bit pentium processor data bus ? ? ? ? provides a 64-bit interface to dram memory ? ? ? ? provides a 32-bit interface to pci ? ? ? ? three integrated posted write buffers and two read buffers increase system performance - 1 level cpu-to-memory posted write buffer (ctmpb) with 4 quadwords (qws) deep - 4 level cpu-to-pci posted write buffer (ctppb) with 4 doublewords (dws) deep - 1 level pci-to-memory posted write buffer (ptmpb) with 1 qw deep - 1 level memory-to-cpu read buffer (crmb) with 1 qw deep - 1 level memory-to-pci read buffer (prmb) with 1 qw deep ? ? ? ? near zero wait state performance on cpu-to-memory and cpu-to-pci writes ? ? ? ? operates synchronously to the 66.7 mhz cpu and 33.3 mhz pci clocks ? ? ? ? provides parity generation for memory writes ? ? ? ? 208-pin pqfp ? ? ? ? 0.6 um cmos technology 3.2 general description the SIS5502 pci local data buffer(pldb) provides a bi-directional data buffering among the 64-bit host data bus, the 64-bit memory data bus, and the 32-bit pci address/data bus. the pldb incorporates three posted write buffers and two read buffers along the bridges of the cpu, pci and memory buses. this buffering scheme smoothes the differences in access latencies and bandwidths among three buses, therefore improves the overall system performance. a four level/4dws deep write buffer (ctppb) provides buffering on cpu write to pci bus. a one level/4qws deep write buffer (ctmpb) is used for buffering write data from the cpu to memory. a one level/1qw deep write buffer (ptmpb) is used to buffer pci write to memory data. a one qw read buffer (crmb) is used to latch cpu read memory data and a one qw read buffer (prmb) is used to latch data in a pci master read from l2 cache or dram cycle. during bus operation between the host, pci and memory, the pldb receives control signals from the pcmc, performs functions such as latching data, forwarding data to destination bus, data assemble and disassemble. figure 3.1 shows the pldb block diagram.
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 77 silicon integrated systems corporation disassemble ctppb (4 dws) l a t c h m u x latch (1 qw) (1dw) disassemble m u x latch & ptmpb 64 32 32 m u x ctmpb (4 qws) l a t c h (1 qw) p.g. p.ck. (1 qw) mdi 64 hdi hdi 32 64 64 64 parity# hgdw adle# prdle hgdw mdle 64 mdi hcr[1:0] md[63:0] pd[7:0] ad[31:0] hd[63:0] prdle prdle figure 3.1 pldb block diagram
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 78 silicon integrated systems corporation 3.3 functional description 3.3.1 data flow between hd bus and md bus ? ? ? ? hd bus to md bus data flows from hd bus to md bus when the cpu writes to local memory or the pcmc writes back a dirty line from the l2 cache to local memory in a cpu read miss/line fill cycle. all the data written to memory are first pushed into the cpmpb. the data are then popped from the buffer and written to memory. ? ? ? ? md bus to hd bu s during a cpu read local memory cycle, the data read are first latched in the 64-bit read buffer (crmb) in order to provide enough hold time for the cpu and the l2 cache. the pldb also checks the parity on the read data. 3.3.2 data flow between hd bus and ad bus ? ? ? ? hd bus to ad bus this path is used in the following two cases. the first case is in a cpu writes pci slave cycle. the second case is in a pci master read cycle that hits modified data in local cache which is implemented using write-back policy. all the cpu data sent to pci memory slave is first pushed into the ctppb. the data are then popped onto the pci ad bus at later time when the pci bus is not busy. any further write to the pci bus is suspended if the ctppb is full. the i/o writes are not posted, but still exploit the ctppb write buffer. the path for pci master read from the l2 cache is implemented through the prmb, a built-in 64-bit pci read memory buffer. since one qw is read each time, the pcmc always sustains 1 wait state for reading the second dw. ? ? ? ? ad bus to hd bu s this path is exercised in two cases. the first case is during cpu reads pci slave and the second case is during pci master write cycles. all the cpu reads pci cycle is stalled until the ctppb is empty. when the cpu reads pci slave, the data are latched and assembled in the ptmpb before they are transmitted to hd bus. during pci master writes to local memory, the pci data are first posted in the ptmpb. they are then transferred to local memory and host bus if the pci master write also hits l2 cache. 3.3.3 data flow between ad bus and md bus ? ? ? ? ad bus to md bus write data from pci master is buffered in ptmpb before transferred to local memory. parity is generated for memory write data. ? ? ? ? md bus to ad bus pci masters receive data from local memory through this path. the prmb, a 64-bit pci read memory buffer is implemented on this path. the read parity is ignored inside the pldb.
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 79 silicon integrated systems corporation 3.3.4 address flow and data flow of basic cycles cycles address flow data flow 1. cpu/r/pci ha ? 5501 ? ad ad ? 5502 ? hd 2. cpu/w/pci ha ? 5501 ? ad hd ? 5502 ? ad 3. cpu/r/isa ha ? 5501 ? ad ? 5503 ? la,sa sd ? 5503 ? ad ? 5502 ? hd 4. cpu/w/isa ha ? 5501 ? ad ? 5503 ? la,sa hd ? 5502 ? ad ? 5503 ? sd 5. cpu/r/dram ha ? 5501 ? ma md ? 5502 ? hd 6. cpu/w/dram ha ? 5501 ? ma hd ? 5502 ? md 7. cpu/r/l2 independent independent 8. cpu/w/l2 independent independent 9. cpu/r/pci(master abort) ha ? 5501 ? ad 5502 ? hd 10. pci/r/l2 ad ? 5501 ? ha hd ? 5502 ? ad 11. pci/w/l2 ad ? 5501 ? ha ad ? 5502 ? hd 12. pci/r/dram ad ? 5501 ? ha md ? 5502 ? ad 13. pci/w/dram ad ? 5501 ? ha ad ? 5502 ? md 14. isa/r/l2 la,sa ? 5503 ? ad ? 5501 ? ha hd ? 5502 ? ad ? 5503 ? sd 15. isa/w/l2 la,sa ? 5503 ? ad ? 5501 ? ha sd ? 5503 ? ad ? 5502 ? hd 16. dma/r/l2 5503 ? ad ? 5501 ? ha, 5503 ? la,sa hd ? 5502 ? ad ? 5503 ? sd 17. dma/w/l2 5503 ? ad ? 5501 ? ha, 5503 ? la,sa sd ? 5503 ? ad ? 5502 ? hd 18. isa/r/dram la,sa ? 5503 ? ad ? 5501 ? ma md ? 5502 ? ad ? 5503 ? sd 19. isa/w/dram la,sa ? 5503 ? ad ? 5501 ? ma sd ? 5503 ? ad ? 5502 ? md 20. dma/r/dram 5503 ? ad ? 5501 ? ma, 5503 ? la,sa md ? 5502 ? ad ? 5503 ? sd 21. dma/w/dram 5503 ? ad ? 5501 ? ma, 5503 ? la,sa sd ? 5503 ? ad ? 5502 ? md 22. isa refresh 5503 ? sa
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 80 silicon integrated systems corporation 3.4 pin assignment and description 3.4.1 pin assignment 45 1 5 10 15 25 35 40 156 155 105 110 120 125 130 135 145 5502 hd9 hd8 hd7 hd6 hd5 hd4 hd3 hd2 vss hd1 hd0 vdd3 md63 md62 md61 md60 md59 md58 md57 md56 md55 vss md53 md54 md52 md51 vdd vss md50 md49 md48 md47 md46 md45 md44 md43 md42 md41 md40 md39 md38 md37 md36 md35 vss md34 md33 md32 pd7 pd6 pd5 pd4 hd55 hd56 hd57 hd58 hd59 hd60 hd61 vss hd62 hd63 vdd3 cpurst ramw # hgdw cppop cppsh adle# cmpop cmpsh mdle prdle adoe parity# hcr0 hcr1 hlda cpuclk vss ad0 ad1 ad2 ad3 vdd ad4 ad5 ad6 ad7 ad8 ad9 ad10 vss ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 81 silicon integrated systems corporation 3.4.2 pin listing ( # means active low) 1=hd9 5v/3.3v 48=md32 5v 95=ad29 5v 2=hd8 5v/3.3v 49=pd7 5v 96=ad28 5v 3=hd7 5v/3.3v 50=pd6 5v 97=ad27 5v 4=hd6 5v/3.3v 51=pd5 5v 98=pciclk 5v 5=hd5 5v/3.3v 52=pd4 5v 99=vss 6=hd4 5v/3.3v 53=md31 5v 100=ad26 5v 7=hd3 5v/3.3v 54=md30 5v 101=ad25 5v 8=hd2 5v/3.3v 55=md29 5v 102=ad24 5v 9=vss 56=md28 5v 103=ad23 5v 10=hd1 5v/3.3v 57=md27 5v 104=ad22 5v 11=hd0 5v/3.3v 58=md26 5v 105=ad21 5v 12=vdd3 5v/3.3v 59=vdd 5v 106=ad21 5v 13=md63 5v 60=md25 5v 107=ad19 5v 14=md62 5v 61=md24 5v 108=ad18 5v 15=md61 5v 62=md23 5v 109=ad17 5v 16=md60 5v 63=vss 110=ad16 5v 17=md59 5v 64=md22 5v 111=ad15 5v 18=md58 5v 65=md21 5v 112=ad14 5v 19=md57 5v 66=md20 5v 113=ad13 5v 20=md56 5v 67=md19 5v 114=ad12 5v 21=md55 5v 68=md18 5v 115=ad11 5v 22=vss 69=md17 5v 116=vss 23=md54 5v 70=md16 5v 117=ad10 5v 24=md53 5v 71=md15 5v 118=ad9 5v 25=md52 5v 72=md14 5v 119=ad8 5v 26=vdd 5v 73=md13 5v 120=ad7 5v 27=md51 5v 74=md12 5v 121=ad6 5v 28=vss 75=md11 5v 122=ad5 5v 29=md50 5v 76=md10 5v 123=ad4 5v 30=md49 5v 77=md9 5v 124=vdd 5v 31=md48 5v 78=md8 5v 125=ad3 5v 32=md47 5v 79=md7 5v 126=ad2 5v 33=md46 5v 80=vss 127=ad1 5v 34=md45 5v 81=md6 5v 128=ad0 5v 35=md44 5v 82=md5 5v 129=vss 36=md43 5v 83=md4 5v 130=cpuclk 5v 37=md42 5v 84=md3 5v 131=hlda 5v 38=md41 5v 85=md2 5v 132=hcr1 5v 39=md40 5v 86=md1 5v 133=hcr0 5v 40=md39 5v 87=md0 5v 134=parity# 5v 41=md38 5v 88=pd3 5v 135=adoe 5v 42=md37 5v 89=pd2 5v 136=prdle 5v 43=md36 5v 90=vdd 5v 137=mdle 5v 44=md35 5v 91=pd1 5v 138=cmpsh 5v 45=vss 92=pd0 5v 139=cmpop 5v 46=md34 5v 93=ad31 5v 140=c ppsh 5v 47=md33 5v 94=ad30 5v 141=cppop 5v
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 82 silicon integrated systems corporation 142=adle# 5v 176=hd38 5v/3.3v 143=hgdw 5v 177=hd37 5v/3.3v 144=ramw# 5v 178=hd36 5v/3.3v 145=cpurst 5v 179=hd35 5v/3.3v 146=vdd3 5v/3.3v 180=hd34 5v/3.3v 147=hd63 5v/3.3v 181=hd33 5v/3.3v 148=hd62 5v/3.3v 182=hd32 5v/3.3v 149=vss 183=vss 150=hd61 5v/3.3v 184=hd31 5v/3.3v 151=hd60 5v/3.3v 185=hd30 5v/3.3v 152=hd59 5v/3.3v 186=hd29 5v/3.3v 153=hd58 5v/3.3v 187=hd28 5v/3.3v 154=hd57 5v/3.3v 188=hd27 5v/3.3v 155=hd56 5v/3.3v 189=hd26 5v/3.3v 156=hd55 5v/3.3v 190=hd25 5v/3.3v 157=hd54 5v/3.3v 191=hd24 5v/3.3v 158=hd53 5v/3.3v 192=hd23 5v/3.3v 159=hd52 5v/3.3v 193=hd22 5v/3.3v 160=vss 194=vss 161=hd51 5v/3.3v 195=hd21 5v/3.3v 162=hd50 5v/3.3v 196=hd20 5v/3.3v 163=hd49 5v/3.3v 197=hd19 5v/3.3v 164=hd48 5v/3.3v 198=vdd3 5v/3.3v 165=hd47 5v/3.3v 199=hd18 5v/3.3v 166=hd46 5v/3.3v 200=hd17 5v/3.3v 167=hd45 5v/3.3v 201=hd16 5v/3.3v 168=hd44 5v/3.3v 202=hd15 5v/3.3v 169=vdd3 5v/3.3v 203=hd14 5v/3.3v 170=hd43 5v/3.3v 204=hd13 5v/3.3v 171=hd42 5v/3.3v 205=hd12 5v/3.3v 172=vss 206=vss 173=hd41 5v/3.3v 207=hd11 5v/3.3v 174=hd40 5v/3.3v 208=hd10 5v/3.3v 175=hd39 5v/3.3v
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 83 silicon integrated systems corporation 3.4.3 pin description pin no. symbol type function 147,148 150-159 161-168 170,171 173-182 184-193 195-197 199-205 207,208 1-8,10,11 hd[63:0] i/o cpu data bus. 13-21,23- 25, 27,29- 44,46-48, 53-58 60-62,64- 79, 81-87 md[63:0] i/o memory data bus. 93-97, 100-115, 117-123 125-128 ad[31:0] i/o pci address/data bus. 91,92,49- 52, 88,89 pd[7:0] i/o parity bit bus. 134 parity# o parity error signal. 135 adoe i drive pci ad bus. this signal is used to enable the 5502 to drive pci ad bus. it is asserted in cpu writes pci or pci master reads local memory cycles. 131 hlda i hold acknowledge is asserted in response to the assertion of cpuhlda. 137 mdle i memory data read latch enable. this signal latches the data on the md bus when negated. 142 adle# i ad bus data latch enable. this signal has the following functions: 1. latch hd or md data into the pci read buffer (prmb) 2. latch ad data into cpu read pci buffer on the rising edge of pciclki. 3. latch ad data into pci posted write buffer (ptmpb) on the rising edge of pciclki.
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 84 silicon integrated systems corporation 140 cppsh i push post write data into the ctppb of the 5502. the data on the hd bus is latched into the ctppb on cppsh rising edge. the edge also increases the write pointer to the next available loading entry in the buffer. 141 cppop i on the rising edge of cppop, the read pointer is changed to address the next available reading location. 138 cmpsh i when this signal is asserted, the data on the hd bus is written into the cpu to memory posted write buffer (ctmpb) on the rising edge of cpuclk, and the write pointer is also changed to address the next available location. 139 cmpop i when this signal is asserted, the read pointer of the ctmpb is increased on the rising edge of cpuclk. 136 prdle i this signal latches the current output entry of the ctppb, the cpu to pci post write buffer, into the prelatch in the 5502. the output of the prelatch is driven to the pci ad bus. in the pci master cycles, prdle is also asserted when pci master is reading data from the secondary cache, or when pci master is writing data to local memory. 143 hgdw i high double word indicator. the signal is driven high by the 5501 when : (1) a high dw from hd bus is written into cpu to pci posted write buffer, (2) the cpu reads a high dw from pci bus, (3) pci master writes a high dw to local memory, (4) pci master reads a high dw from local memory. 132,133 hcr[1:0] i host data bus control. these signals are driven by the 5501 and they are used to control the 5502 hd[63:0] bus. they are defined as: 00: 5502 floats hd bus 01: 5502 drives ffffffff to hd bus 10: 5502 drives data from ad bus to hd bus 11: 5502 drives data from md bus to hd bus 144 ramw# i dram write enable. 145 cpurst i cpu reset. 130 cpuclk i cpu clock. 98 pciclk i pci bus clock. 26,59,90, 124 vdd +5v dc power
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 85 silicon integrated systems corporation 12, 146, 169, 198 vdd3 +3.3v dc power in 3v system +5v dc power in 5v system 9,22,28,45 ,63,80,99, 116,129, 149,160 172,183, 194,206 vss ground 3.5 electrical characteristics 3.5.1 absolute maximum ratings parameter min max unit ambient operating temperature 0 70 o c storage temperature -40 125 o c input voltage -0.3 5.5 v output voltage -0.5 5.5 v power dissipation 1 w note: stress above these listed may cause permanent damage to device. functional operation of this device should be restricted to the conditions described under operating conditions. 3.5.2 dc characteristics ta = 0 - 70 o c, vss = 0v , vdd=5v+5%, vdd3=3.3v+ 5% symbol parameter min max unit condition v il 1 input low voltage -0.3 0.8 v note 1 , vdd3=3.3v v ih1 input high voltage 2.2 vdd3+0.3v v note 1 v il2 input low voltage -0.3 0.8 v note 2 v ih2 input high voltage 2.2 vdd+0.3 v note 2 v ol1 output low voltage 0.45 v note 3 v oh1 output high voltage 2.4 v note 3 v ol2 output low voltage 0.4 v note 4 v oh2 output high voltage 2.0 vdd3 v note 4 i ol1 output low current 4 ma note 5 i oh1 output high current 4 ma note 5 i ih input leakage current +10 ma i il input leakage current -10 ma c in input capacitance 12 pf fc=1 mhz c out output capacitance 12 pf fc=1 mhz c i/o i/o capacitance 12 pf fc=1 mhz icc3 power supply current of vdd3 27 ma 3.3v, 66mhz
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 86 silicon integrated systems corporation note: 1. v il 1 and v ih1 are applicable to hd[63:0]. 2. v il2 and v ih2 are applicable to md[63:0], ad[31:0], cpurst, pd[7:0], cpuclk, adoe, hlda, hcr[1:0], prdle, mdle, cmpsh, cmpop, cppsh, cppop, adle#, hgdw, ramw#. 3. v ol1 and v oh1 are applicable to md[63:0], ad[31:0], pd[7:0], parity#. 4. v ol2 and v oh2 are applicable to hd[31:0]. 5. i ol1 and i oh1 are applicable to hd[63:0], md[63:0], ad[31:0], pd[7:0], parity#. 3.5.3 ac characteristics symbol parameter min typ max fig t1 md data setup time to mdle falling 6 3.2, 3.9 t2 md data hold time to mdle falling 2 3.2, 3.9 t3 hd data valid delay from md data valid 10 15 3.2 t4 adle# setup time to pciclk rising 6 3.3,3.8 t5 adle# hold time to pciclk rising 2 3.3,3.8 t6 hgdw setup time to pciclk rising 6 3.3,3.8 t7 hgdw hold time to pciclk rising 2 3.3,3.8 t8 ad data setup time to pciclk rising 6 3.3,3.8 t9 ad data hold time to pciclk rising 2 3.3,3.8 t10 hd data valid delay from pciclk rising 10 15 3.3,3.8 t11 cmpsh setup time to cpuclk rising 6 3.4 t12 cmpsh hold time to cpuclk rising 2 3.4 t13 cmpop setup time to cpuclk rising 6 3.4 t14 cmpop hold time to cpuclk rising 2 3.4 t15 hd data setup time to cppsh rising 6 3.4,3.5 t16 hd data hold time to cppsh rising 2 3.4,3.5 t17 md data valid delay from cpuclk rising 12 20 3.4 t18 pd data valid delay from cpuclk rising 15 25 3.4 t19 ramw# setup time to mdle rising 3.7 t20 ramw# hold time to mdle falling 3.7 t21 parity# active delay from mdle falling 6 9 3.7 t22 ad data valid from prdle rising 7 11 3.6 t23 ad data valid from md data valid 12 18 3.10 t24 hgdw setup time to cppsh rising 6 3.5 t25 hgdw hold time to cppsh rising 2 3.5 t26 md data valid delay from pciclk rising 12 18 3.8 t27 pd data valid delay from pciclk rising 15 23 3.8 t28 hd data setup time to adle# falling 6 3.9 t29 hd data hold time to adle# falling 2 3.9 t30 ad data valid delay from hd data valid 12 18 3.9 t31 md output delay from ramw# asserted 5 7.5 3.11
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 87 silicon integrated systems corporation t32 md output float delay from ramw# inactive 25 43 3.11 t33 ad output delay from adoe asserted 4 6 3.12 t34 ad output float delay from adoe inactive 26 3.12 t35 hd output delay from hcr asserted 6 9 3.13 t36 hd output float delay from hcr inactive 3.13 unit :ns 3.5.4 ac timing diagram mdle md hd t1 t2 t3 figure 3.2 cpu read dram cycle pciclk adle# e hgdw ad hd t4,t6 t5,t7 t8 t9 t10 figure 3.3 cpu read pci slave cycle cpuclk cmpsh cmpop hd md pd t11,t13 t12,t14 t15 t16 t17 t18 figure 3.4 cpu write dram cycle cppsh hd t24 t25 t15 t16 hgdw figure 3.5 cpu write pci post write buffer
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 88 silicon integrated systems corporation prdle ad t22 figure 3.6 write posted data onto pci bus t19 t20 t21 mdle ramw# parity# figure 3.7 parity# generation reading dram cycle pciclk adle# hgdw ad hd md pd t4,t6 t5,t7 t8 t9 t10 t26 t27 figure 3.8 cpu read pci slave cycle adle# hd ad t28 t29 t30 figure 3.9 pci master read secondary cache mdle adle# md ad t1 t2 t23 figure 3.10 pci master read dram
SIS5502 pci local data buffer preliminary v2.0 april 2, 1995 89 silicon integrated systems corporation t31 t32 ramw# md figure 3.11 cpu write dram cycle t33 t34 adoe ad figure 3.12 write posted data onto pci bus t35 t36 hcr hd figure 3.13 cpu read dram or pci cycle
sis5503 pci system i/o preliminary v2.0 april 2, 1995 90 silicon integrated systems corporation 4 sis5503 4.1 features ? ? ? ? integrated bridge between pci bus and isa bus - translates pci bus cycles into isa bus cycles - translates isa master or dma cycles into pci bus cycles - provides pci-to-isa memory one doubleword posted write buffer ? ? ? ? integrated isa bus compatible logic - isa bus controller - isa arbiter for isa master, dma devices, and refresh - built-in two 8237 compatible dma controllers - built-in two 8259a compatible interrupt controllers - built-in one 8254 timer ? ? ? ? supports reroutibilty of four pci interrupts to any unused irq interrupt ? ? ? ? supports flash rom ? ? ? ? built-in rtc with 242 bytes extended cmos sram ? ? ? ? built-in pci ide - fully compatible with pci local bus specification v2.0. - accommodates 8 bits, 16 bits, and 32 bits data transfer. - supports pci burst read/write operation. - supports read ahead & posted write buffers for concurrent system operation. - controls two ide channels and max. connects 4 ide drives. - supports pio mode 3 timing ide specification. - programmable command and recovery timing for reads and writes per channel. - auto ide channel speed setting with software driver. - hardware and software chip disable capability - supports power down feature ? ? ? ? meet pci specification buffer strength ? ? ? ? 160-pin pqfp ? ? ? ? 0.6 m cmos technology 4.2 functional description the sis5503 is a highly integrated pci/isa system i/o (psio) device that integrates all the necessary system control logic used in pci/isa specific applications. the sis5503 consists of: a pci bridge that translates pci cycles onto isa bus, and isa master/dma device cycles onto pci bus; a seven-channel programmable dma controller, a sixteen-level programmable interrupt controller, a programmable timer with three counters, a built-in rtc with 242 bytes extended cmos sram, and a built-in pci ide. since 5503 includes a pci to isa bridge and a pci ide, it naturally becomes a multifunction device. the pci/isa bridge is defined as function 0 device while pci ide is function 1 device. the following two examples describe how to write register xx in pci to isa bridge configuration space and register yy in pci ide configuration space.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 91 silicon integrated systems corporation example 1: mov eax, 800010xxh out 0cf8h, eax mov al, data out 0cfdh, al example 2: mov eax, 800011yyh out 0cf8h, eax mov al, data out 0cfdh, al 4.2.1. pci bridge the sis5503 pci bus interface provides the interface between psio and the pci bus. it contains both pci master and slave bridge to the pci bus. when siognt# is asserted, the master bridge translates the isa master or dma cycles onto the pci bus based on the decoding status from isa address decoder. when siognt# is negated, the slave bridge accepts these cycles initiated on the pci bus targeted to the psio internal registers or isa bus, and then forwards the cycles to the isa bus interface that further translates them onto the isa bus. the pci address decoder provides the information on which the slave bridge depends to respond and process the cycle initiated by pci masters. pci slave bridge as a pci slave, psio responds to both i/o and memory transfers. psio always target- terminates after the first data phase for any bursting cycle. sis5503 always converts the single interrupt acknowledge cycle (from 5501) into two cycles that the internal 8259 pair can respond to. the psio is assigned as the subtractive decoder in the bus 0 of the sis pci/isa system by accepting all accesses not positively decoded by some other agent. in reality, the psio only subtractively responds to low 64k i/o or low 16m memory accesses. psio also positively decodes i/o addresses for internal registers, and bios memory space by asserting devsel# on the medium timing. pci master bridge as long as siognt# is asserted, the pci master bridge on behalf of dma devices or isa masters starts to drive the ad bus, c/be[3:0]# and par signal. when mrdc# or mwtc# is asserted, the psio will generate frame#, and irdy# to pci bus if the targeted memory is not on the isa side. the valid address and command are driven during the address phase, and par is asserted one clock after that phase. psio always activated frame# for 2 pclks because it does not conduct any bursting cycle.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 92 silicon integrated systems corporation the isa address decoder is used to determine the destination of isa master or dma devices. this decoder provides the following options as they are defined in configuration registers 48 to 4b. a. memory: 0-512k b. memory: 512k-640k c. memory: 640k-768k(video buffer) d. memory: 768k-896k in eight 16k sections(expansion rom) e. memory: 896k-960k(lower bios area) f. memory: 1m-xm-16m within which a hole can be opened. access to the hole is not forwarded to pci bus. g. memory:>16mb automatically forwards to pci. 4.2.2 isa bus controller the sis5503 isa bus interface accepts those cycles from pci bus interface and then translates them onto the isa bus. it also requests the pci master bridge to generate pci cycle on behalf of dma or isa master. the isa bus interface thus contains a standard isa bus controller and a data buffering logic. ibc provides all the isa control, such as isa command generation, i/o recovery control, wait-state insertion, and data buffer steering. the pci to/from isa address and data bus bufferings are also all integrated in sis5503. the sis5503 can directly support six isa slots without external data or address buffering. standard isa bus refresh is requested by counter 1, and then performed via the ibc. ibc generates the pertinent command and refreshes address to the isa bus. since the isa refresh is transparent to the pci bus and the dma cycle, an arbiter is employed to resolve the possible conflicts among pci cycles, refresh cycles, and dma cycles. 4.2.3 dma controller the sis5503 contains a seven-channel dma controller. the channel 0 to 3 is for 8-bit dma devices while channel 5 to 7 is for 16-bit devices. the channels can also be programmed for any of the four transfer modes, which include single, demand, block, and cascade. except in cascade mode, each of the three active transfer modes can perform three different types of transfers, which include read, write, and verify. the address generation circuitry in sis5503 can only support 24-bit address for dma devices. 4.2.4 interrupt controller the sis5503 provides an isa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the two controllers are cascaded so that 14 external and two internal interrupts are supported. the master interrupt controller provides irq<7:0> and the slave one provides irq<15:8>. the two internal interrupt are used for internal functions only and are not available externally. irq2 is used to cascade the two controllers together and irq0 is used as a system timer interrupt and is tied to interval counter 0. the remaining 14 interrupt lines are available for external system interrupts.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 93 silicon integrated systems corporation priority label controller typical interrupt source 1 irq0 1 timer/counter 0 out 2 irq1 1 keyboard 3-10 irq2 1 interrupt from controller 2 3 irq8# 2 real time clock 4 irq9 2 expansion bus pin b04 5 irq10 2 expansion bus pin d03 6 irq11 2 expansion bus pin d04 7 irq12 2 expansion bus pin d05 8 irq13 2 coprocessor error ferr# 9 irq14 2 fixed disk drive controller expansion bus pin d07 10 irq15 2 expansion bus pin d06 11 irq3 1 serial port 2, expansion bus b25 12 irq4 1 serial port 1, expansion bus b24 13 irq5 1 parallel port 2, expansion bus b23 14 irq6 1 diskette controller, expansion bus b22 15 irq7 1 parallel port, expansion bus b21 in addition to the isa features, the ability to do interrupt sharing is included. two registers(eclr) located at 4d0h and 4d1h are defined to allow edge or level sense selection to be made on an individual channel by channel basis instead of on a complete bank of channels. note that the default of irq0, irq1, irq2, irq8# and irq13 is edge sensitive, and can not be programmed. also, each pci interrupt(intx#) can be programmed independently to route to one of the eleven isa compatible interrupts(irq<7:3>, irq<15:14>, and irq<12:9>) through configuration registers 41h to 44h. 4.2.5 timer/counter the sis5503 contains 3 channel counter/timer that is equivalent to those found in the 82c54 programmable interval timer. the counters use a division of 14.31818mhz osc input as the clock source. the outputs of the timers are directed to key system functions. counter 0 is connected to the interrupt controller irq0 and provides a system timer interrupt for a time-of- day, diskette time-out, or the other system timing function. counter 1 generates a refresh- request signal and counter 2 generates the tone for the speaker. 4.2.6 built-in rtc the 5503 incorporates a real-time clock and system configuration memory. the rtc combines: ? a complete time-of-day clock with alarm ? 100 year calendar ? programmable periodic interrupt ? 14 bytes of clock and control registers and 242 bytes of lower power general purpose sram
sis5503 pci system i/o preliminary v2.0 april 2, 1995 94 silicon integrated systems corporation the method of accessing the upper 128 bytes of cmos sram is to write 80h to i/o port 22h and then setting bit 3 of i/o port 23h. 4.2.7 built-in pci ide the internal pci ide contains five blocks. they are pci bus interface and decode, system configuration & control, ide interface ckt, read ahead buffers, and posted write buffers. pci bus interface and decode the internal pci ide operates as a slave device. it decodes and interprets pci cycles and generate signals to start and terminate ide cycles. this block responds only to cycles that belong to ide i/o address space. it supports both 16- bit and 32-bit i/o data transfer at address 1f0/170. all other ide registers r/w are 8-bit only. system configuration & control & pci configuration this block contains pci configuration header and registers to meet pci specifications. the internal pci ide supports pci type 0 configuration cycles of configuration mechanism #1. ide interface ckt proper cycle timing is generated to fit pci bus speed and different mode of ide drive. all cycle timing can be controlled by software programming. posted write buffers & read ahead buffers the internal pci ide has two kinds of buffers, posted write buffers and read ahead buffers. they can be enabled or disabled independently. the posted write buffers can enhance the transfer rate of the pci bus interface to ide interface write operation by decoupling the wait-states effect from the slower ide side to the faster pci bus side. the read ahead buffers can eliminate the idle cycle of the pci bus side to improve read operation.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 95 silicon integrated systems corporation 4.3 functional block diagram wakeup0 pciclk pcirst# ad[31:0] c/be[3:0]# frame# trdy# irdy# stop# lock# devsel# serr# par int a-d# sioreq# siognt# pci bus interface irq(15,14, 12:9,7:3,1) ferr# int nmi wapeup1 interrupt controller spkr timers/counters data buffer pci decoder isa decoder sd[15:8] sa[16:0] la[23:17] io16# m16# sbe# mr16# mrdc# mwtc# aen chrdy iochk# bclk bale iorc# iowc# smrdc# smwtc# zws# osc rtcale rtcrd rtcwr ref# romkbcs# sdir ignne# isa bus interface drq[7:5,3:0] dak[2:0] eop dma controller xd[7:0] irq8 rtc *rtcvdd *osci *psrstb# *pwrgd pci ide *id[15:0] *idecs[3:0]# * : multi-function pin figure 4.1 sis5503 functional block diagram
sis5503 pci system i/o preliminary v2.0 april 2, 1995 96 silicon integrated systems corporation 4.4 configuration registers registers 00h, 01h vid - vendor identification register bits 15:0 1039h (read only) registers 02h, 03h did - device identification register bits 15:0 0008h (read only) registers 04h, 05h com - command register = 07h bits 15:4 reserved. read as 0's bit 3 sce (special cycle enable) = 0 bit 2 bme (bus master enable) = 1 bit 1 mse (memory space enable) = 1 bit 0 iose (i/o space enable) = 1 registers 07h-06h ds - device status register bits 15:14 reserved. read as 0's bit 13 ma (master-abort status). when the 5503 generates a master-abort, ma is set to a 1. software clears ma to 0 by writing a 1 to this bit location. bit 12 rta (received target-abort status). when the 5503 receives a target-abort, rta is set to a 1. software clears rta to 0 by writing a 1 to this bit location. bit 11 reserved. read as a 0 bits 10:9 devt (sio devsel# timing status). the 5503 always generates devsel# with medium timing, devt=01 bits 8:0 reserved. read as 0's. register 08h rid - revision identification register bits 7:0 00h (read only) register 0b-09h class code bits 23:0 060100h (read only) register 0eh header type
sis5503 pci system i/o preliminary v2.0 april 2, 1995 97 silicon integrated systems corporation bits 7:0 80h register 40h bioscon - bios control register bit 7 reserved. read as a 0. bit 6 reserved. read as a 0. bit 5 when isa master retries, arbiter deasserts siognt#. this bit defaults to 0. bit 4 pci posted write buffer enable the default value is 0 (disabled). bits [3:0] determine how the 5503 responds to f segment, e segment, and extended segment (fff80000-fffdffff) accesses. 5503 will positively respond to extended segment access when bit 0 is set. bit 1, combining with bits [3:2], enables 5503 to respond to e segment access. bit 3 positive decode of upper 64k byte bios enable. bit 2 bios subtractive decode enable. bits [3:2] f segment e segment comment +-+- 00 * 5503 positively responds to e segment access. 01 5503 subtractively responds to f segment access. 10 ? * 5503 positively responds to e and f segment access. 11 5503 positively responds to f segment access. *: enabled if bit 1 is set. bit 1 lower bios enable. bit 0 extended bios enable. (fff80000~ fffdffff) register 41h inta# remapping control register bit 7 remapping control when enabled, inta#, is remapped to the pc compatible interrupt signal specified in irq remapping table. this bit is set to 1 after reset. 0: enable 1: disable bits 6:4 reserved. read as 0's.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 98 silicon integrated systems corporation bits 3:0 irqx remapping table. bits irqx# bits irqx# bits irqx# bits irqx# 0000 reserved 0101 irq5 1010 irq10 1111 irq15 0001 reserved 0110 irq6 1011 irq11 0010 reserved 0111 irq7 1100 irq12 0011 irq3 1000 reserved 1101 reserved 0100 irq4 1001 irq9 1110 irq14 register 42h intb# remapping control register bit 7 remapping control bits 6:4 reserved. read as 0's. bits 3:0 irq remapping table. register 43h intc# remapping control register bit 7 remapping control bits 6:4 reserved. read as 0's. bits 3:0 irq remapping table. register 44h intd# remapping control register bit 7 remapping control bits 6:4 reserved. read as 0's. bits 3:0 irq remapping table. note: the difference int[a:d]# can be remapped to the same irq signal, but this irq signal should be set to level sensitive. register 48h isa master/dma memory cycle control register 1 the isa master or dma memory access cycles will be forwarded to pci bus when the address fall within the programmable region defined by bits[7:4]. the base address of the programmable region is 1mbyte, and the top addresses is programmed in 1mbyte increments from 1mbyte to 16mbyte. all memory cycles will be forwarded to pci bus besides the cycle fall within memory hole defined in register 4ah and 4bh. bits 7:4 bits 7 6 5 4 top of memory 0 0 0 0 1 mbyte
sis5503 pci system i/o preliminary v2.0 april 2, 1995 99 silicon integrated systems corporation 0 0 0 1 2 mbyte 0 0 1 0 3 mbyte 0 0 1 1 4 mbyte 0 1 0 0 5 mbyte 0 1 0 1 6 mbyte 0 1 1 0 7 mbyte 0 1 1 1 8 mbyte 1 0 0 0 9 mbyte 1 0 0 1 10 mbyte 1 0 1 0 11 mbyte 1 0 1 1 12 mbyte 1 1 0 0 13 mbyte 1 1 0 1 14 mbyte 1 1 1 0 15 mbyte 1 1 1 1 16 mbyte isa master and dma memory cycles to the following memory regions will be forwarded to pci bus if they are enabled. bit 3 f0000h~e ffffh memory region 0: disable 1: enable, the cycle is forwarded to pci bus. bit 2 a0000h~b ffffh memory region 0: disable 1: enable, the cycle is forwarded to pci bus. bit 1 80000h~9 ffffh memory region 0: disable 1: enable the cycle is forwarded to pci bus. bit 0 00000h~7 ffffh memory region 0: disable 1: enable the cycle is forwarded to pci bus. register 49h isa master/dma memory cycle control register 2 isa master and dma memory cycles to the following memory regions will be forwarded to pci bus if they are enabled. bit 7 dc000h-d ffffh memory region 0: disable
sis5503 pci system i/o preliminary v2.0 april 2, 1995 100 silicon integrated systems corporation 1: enable bit 6 d8000h-db fffh memory region 0: disable 1: enable bit 5 d4000h-d7 fffh memory region 0: disable 1: enable bit 4 d0000h-d3 fffh memory region 0: disable 1: enable bit 3 cc000h-c ffffh memory region 0: disable 1: enable bit 2 c8000h-cb fffh memory region 0: disable 1: enable bit 1 c4000h-c7 fffh memory region 0: disable 1: enable bit 0 c0000h-c3 fffh memory region 0: disable 1: enable register 4ah isa master/dma memory cycle control register 3 register 4ah and register 4bh are used to define the isa address hole. the isa address hole is located between 1mbyte and 16mbyte, and sized in 64kbyte increments. isa master and dma memory cycles fall within this hole will not be forwarded to pci bus. register 4ah and 4bh are used to define the bottom and top address of the hole respectively. the hole is located between top and bottom address, and the bottom and top address must be at or above 1mbyte. if bottom address is greater than top address, the isa address hole is disabled. bit 7 a23 bit 6 a22 bit 5 a21
sis5503 pci system i/o preliminary v2.0 april 2, 1995 101 silicon integrated systems corporation bit 4 a20 bit 3 a19 bit 2 a18 bit 1 a17 bit 0 a16 register 4bh isa master/dma memory cycle control register 4 this register is used to define the top address of the isa address hole. bit 7 a23 bit 6 a22 bit 5 a21 bit 4 a20 bit 3 a19 bit 2 a18 bit 1 a17 bit 0 a16 registers 4ch-4fh bits 7:0 icw1 to icw4 of the built-in interrupt controller (master) can be read from 4ch to 4fh. registers 50h-53h bits 7:0 icw1 to icw4 of the built-in interrupt controller (slave) can be read from 50h to 53h. registers 54h-55h bits 7:0 ocw2 to ocw3 of the built-in interrupt controller (master) can be read from 54h to 55h. registers 56h-57h bits 7:0 ocw2 to ocw3 of the built-in interrupt controller (slave) can be read from 56h to 57h. register 58h bits 7:0 low byte of the initial count number of counter 0 in the built-in ctc can be read from 58h.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 102 silicon integrated systems corporation register 59h bits 7:0 high byte of the initial count number of counter 0 in the built-in ctc can be read from 59h. register 5ah bits 7:0 low byte of the initial count number of counter 1 in the built-in ctc can be read from 5ah. register 5bh bits 7:0 high byte of the initial count number of counter 1 in the built-in ctc can be read from 5bh. register 5ch bits 7:0 low byte of the initial count number of counter 2 in the built-in ctc can be read from 5ch. register 5dh bits 7:0 high byte of the initial count number of counter 2 in the built-in ctc can be read from 5dh. register 5eh bits 7:0 control word (43h) of the built-in ctc can be read from 5eh. register 5fh bits 7:0 indicates the status whether the lsb or msb is read or written when read/write word function has been processed for the corresponding counter. 4.5 non-configuration registers dma registers these registers can be accessed from pci bus. address attribute register name 0000h r/w dma1 ch0 base and current address register 0001h r/w dma1 ch0 base and current count register 0002h r/w dma1 ch1 base and current address register 0003h r/w dma1 ch1 base and current count register 0004h r/w dma1 ch2 base and current address register 0005h r/w dma1 ch2 base and current count register 0006h r/w dma1 ch3 base and current address register 0007h r/w dma1 ch3 base and current count register 0008h r/w dma1 status(r) command(w) register
sis5503 pci system i/o preliminary v2.0 april 2, 1995 103 silicon integrated systems corporation 0009h wo dma1 request register 000ah wo dma1 write single mask bit 000bh wo dma1 mode register 000ch wo dma1 clear byte pointer 000dh wo dma1 master clear 000eh wo dma1 clear mask register 000fh r/w dma1 write all mask bits(w) mask status register(r) 00c0h r/w dma2 ch0 base and current address register 00c2h r/w dma2 ch0 base and current count register 00c4h r/w dma2 ch1 base and current address register 00c6h r/w dma2 ch1 base and current count register 00c8h r/w dma2 ch2 base and current address register 00cah r/w dma2 ch2 base and current count register 00cch r/w dma2 ch3 base and current address register 00ceh r/w dma2 ch3 base and current count register 00d0h r/w dma2 status(r) command(w) register 00d2h wo dma2 request register 00d4h wo dma2 write single mask bit register 00d6h wo dma2 mode register 00d8h wo dma2 clear byte pointer 00dah wo dma2 master clear 00dch wo dma2 clear mask register 00deh r/w dma2 write all mask bits(w) mask status register(r) these registers can be accessed from pci bus or isa bus. address attribute register name 0080h r/w reserved 0081h r/w dma channel 2 low page register 0082h r/w dma channel 3 low page register 0083h r/w dma channel 1 low page register 0084h r/w reserved 0085h r/w reserved 0086h r/w reserved 0087h r/w dma channel 0 low page register 0088h r/w reserved 0089h r/w dma channel 6 low page register 008ah r/w dma channel 7 low page register 008bh r/w dma channel 5 low page register 008ch r/w reserved 008dh r/w reserved 008eh r/w reserved 008fh r/w refresh low page register
sis5503 pci system i/o preliminary v2.0 april 2, 1995 104 silicon integrated systems corporation
sis5503 pci system i/o preliminary v2.0 april 2, 1995 105 silicon integrated systems corporation interrupt controller registers (these registers can be accessed from pci bus or isa bus.) address attribute register name 0020h r/w int 1 base address register 0021h r/w int 1 mask register 00a0h r/w int 2 base address register 00a1h r/w int 2 mask register timer registers (these registers can be accessed from pci bus or isa bus.) address attribute register name 0040h r/w interval timer 1 - counter 0 0041h r/w interval timer 1 - counter 1 0042h r/w interval timer 1 - counter 2 0043h wo interval timer 1 - control word register other registers (these registers can be accessed from pci bus or isa bus.) address attribute register name 0061h r/w nmi status register 0070h wo cmos ram address and nmi mask register 00f0h wo coprocessor error register register 4d0h irq edge/level control register 1 bit 7 irq7 0: edge sensitive 1: level sensitive bit 6 irq6 0: edge sensitive 1: level sensitive bit 5 irq5 0: edge sensitive 1: level sensitive bit 4 irq4 0: edge sensitive 1: level sensitive bit 3 irq3 0: edge sensitive 1: level sensitive
sis5503 pci system i/o preliminary v2.0 april 2, 1995 106 silicon integrated systems corporation bit 2 irq2 this bit must be set to 0. read as 0. bit 1 irq1 this bit must be set to 0. read as 0. bit 0 irq0 this bit must be set to 0. read as 0. after reset this register is set to 00h. register 4d1h irq edge/level control register 2 bit 7 irq15 0: edge sensitive 1: level sensitive bit 6 irq14 0: edge sensitive 1: level sensitive bit 5 irq13 this bit must be set to 0. read as 0. bit 4 irq12 0: edge sensitive 1: level sensitive bit 3 irq11 0: edge sensitive 1: level sensitive bit 2 irq10 0: edge sensitive 1: level sensitive bit 1 irq9 0: edge sensitive 1: level sensitive bit 0 irq8 this bit must be set to 0. read as zero. after reset this register is set to 00h.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 107 silicon integrated systems corporation 4.6 isa internal register isa internal registers are accessed through an address/data registers pair. address register located at port 22h is written with the index of isa internal register. then isa internal register content can be read or written through the data register at port 23h. the port 22h can be read to get the last written-in value. register 80h bits 7:6 bus clock selection 00: 7.159mhz 01: pciclk/4 10: pciclk/3 bit 5 flash eprom control bit 0 (please refer to register 80h bit 2 for details.) bit 4 programmable output pin 0: pin 20 is used as wakeup0 when internal ide is disabled 1: pin 20 is used as "programmable output pin" that can generate one write pulse by writing register 82h when internal ide is disabled bit 3 access upper 128 bytes cmos sram 0: disable 1: enable bit 2 flash eprom control bit 1 previous implementation on flash eprom support limits that eprom is flashed upon power on till bit 5 of register 80h is set to 1. the new added feature will allow eprom to be flashed anytime. bit 2 of the register 80h is added and the setting of both bit 2 and bit 5 will now control the eprom flash operation. register 80h bit 5 register 80h bit 2 operation 0 0 eprom can be flashed 1 0 eprom can't be flashed again x 1 eprom can be flashed whenever bit 5 is 0 bit 1 relocatable isa configuration registers control isa configuration registers are now relocatable through bit 1 of isa configuration register 80h. upon power on, isa configuration registers are located between index 80h to 8fh by default. these index can be relocated to 70h to 7fh by programming bit 1 of register 80h to 1.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 108 silicon integrated systems corporation bit 0 isa slew rate control the default value of the following isa signals is 8ma(min), including sa[16- 0], la[23-17], sbhe#, mrdc#, mwtc#, smrdc#, smwtc#, iorc#, and iowc#. besides, bit 0 of isa configuration register 80h is used to program the currents of the above signals to 12ma(min) when it is set to 1. register 81h bits 7:6 16-bit i/o cycle command recovery time 00 : 5 busclk 01 : 4 busclk 10 : 3 busclk 11 : 2 busclk bits 5:4 8-bit i/o cycle command recovery time 00 : 8 busclk 01 : 5 busclk 10 : 4 busclk 11 : 3 busclk bit 3 reserved bit 2 16-bit memory, i/o wait state selection 0 : 1 wait state 1 : 0 wait state bit 1 internal pci ide enable/disable 0: enable 1: disable this function is available only when the internal pci ide is enabled by hardware tarp, pull sdir# high. bit 0 reserved register 82h if this register is written by any values, the pin 20 will generate one write pulse when bit 4 of register 80h "programmable output pin" is enabled register 83h bits 7:2 reserved bit 1 isa bus refresh cycle enable/disable
sis5503 pci system i/o preliminary v2.0 april 2, 1995 109 silicon integrated systems corporation 0: enable 1: disable bit 0 pci output and bidirectional buffers current selection 0: 50ma/2.2v (default value) 1: 95ma/2.2v register 84h bios register bits 7:0 bios can use this register to store data. register 85h bits 7:0 the same value as port 70h. register 88h bits 7:1 corresponds to the mask bits of the irq7-1. when disabled, any event from the corresponding irq will cause the system to exit the system standby state. bit 0 is the mask bit of the nmi. when disabled, an event from the nmi will cause the system to exit the system standby state. register 89h bits 7:0 corresponds to the mask bits of the irq8-15. when disabled, any event from the corresponding irq will cause the system to exit the system standby state. register 8ah bits 7:1 corresponds to the mask bits of the irq7-1. when disabled, any event from the corresponding irq will cause the system to exit the monitor standby state. bit 0 is the mask bit of the nmi. when disabled, an event from the nmi will cause the system to exit the monitor standby state. register 8bh bits 7-0 corresponds to the mask bits of the irq8-15. when disabled, any event from the corresponding irq will cause the system to exit the monitor standby state.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 110 silicon integrated systems corporation 4.7 pci ide configuration registers 31 16 15 0 device id = 0601h vendor id = 1039h 00h status = 0000-0000-0000-0000 command = 0000-0000-1000-1001 04h base class = 01h sub-class = 01h prog. if = 00h revision id = 00h 08h bist = 00h header type = 80h latency timer = 00h cache line size = 00h 0ch xxxx17xx 0 1 10h xxxx1fxx 0 1 14h xxxx37xx 0 1 18h xxxx3fxx 0 1 1ch reserved (00000000) 0 1 20h reserved (00000000) 0 1 24h reserved (00000000) 28h reserved (00000000) 2ch expansion rom base address none (00000000) 30h reserved (00000000) 34h reserved (00000000) 38h max_lat = 00h min_gnt = 00h interrupt pin = 00h interrupt line 3ch register 40h built-in pci ide control register 1 bit 7 ide channel and address select bit 0 bit 6 auto power down mode 0: disable 1: enable bits 5:3 channel 1 wait state (b2-b0) bits 2:0 channel 0 wait state (b2-b0) read (pciclks) write (pciclks) wait-state b3b2b1b0 recovery active recovery active st. 1 1st 1 2nd 1 st. 1st 2nd 000 5 4 3 3 7654 001 5 4 3 4 11 10 9 4 010 5 4 3 6 11 10 9 6 011 7 6 5 6 13 12 11 6
sis5503 pci system i/o preliminary v2.0 april 2, 1995 111 silicon integrated systems corporation 100 7 6 5 8 13 12 11 8 101 9 8 7 8 15 14 13 8 110 11 10 9 8 19 18 17 8 111(default) 13 12 11 8 19 18 17 8 note : 1. st. means standard mode, 1st means 1st enhanced mode and 2nd means 2nd enhanced mode. for the detailed information, please refer to "register 41h". 2. the above table contains normal cycle timing. when the read ahead buffers and posted write buffers are enabled, the cycle time for read cycle is 4t, and for write cycle, 6t. register 41h built-in pci ide control register 2 bits 7 post write buffer 0: disable 1: enable bit 6 reserved, must be "1" bit 5 reserved, must be "0" bit 4 1st enhanced speed mode (recovery time = standard speed - 1t) 0: disable 1: enable bit 3 address remapping 0: disable 1: enable bit 2 read prefetch buffer 0: disable 1: enable bit 1 2nd enhanced speed mode (recovery time = 1st enhanced speed - 1t) 0: disable 1: enable bit 0 ide channel and address select bit 1 reg. 41h bit 0 reg. 40h bit 7 0 0 ch0 1fx, 3f6 only(idecs0, idecs1) 0 1 ch0 17x, 376 only(idecs0, idecs 1) 1 0 ch0 1fx, 3f6/ch1 17x, 376(idecs0, idecs1, idecs2, idecs3) 11reserved
sis5503 pci system i/o preliminary v2.0 april 2, 1995 112 silicon integrated systems corporation 4.8 pin assignment and description 4.8.1 hardware trap pin no. symbol description 116 sdir# to enable the internal ide, this signal needs to be pulled high via a 10k ohms resistor. reversly, if this signal is pulled low, the internal ide is disabled. 9 romkbcs# if super i/o device with built-in rtc is used, this signal should be connected gnd via a 10k ohms resistor. 13 rtcale/pwrgd this signal is an input pin upon power up. 5503 will strobe this pin on the rising edge of pcirst# to identify that internal or external rtc is used. if this signal is sampled high, internal rtc is used. on the other hand, if it is sampled low(as signal of external rtc is pulled low via a 4.7k ohms resistor), external rtc is employed. the actual function of multi-function pins in various configuration is summarized as follows: 5503 rtc 5503 ide ext. rtc sio rtc pin 13 pin 12 pin 11 pin 10 pin 20 ? pwrgd psrstb# idecyc# osci wakeup0 gcs pwrgd psrstb# undef. osci wakeup0 gcs ? undef. undef. idecyc# irq8# wakeup0 gcs ? rtcale rtcrd# rtcwr# irq8# idecyc# rtcale rtcrd# rtcwr# irq8# wakeup0 gcs undef. undef. undef. irq8# wakeup0 gcs
sis5503 pci system i/o preliminary v2.0 april 2, 1995 113 silicon integrated systems corporation 4.8.2 pin assignment 1 5 10 15 25 35 40 5503 81 85 90 95 100 105 110 115 120 xd3 xd2 xd1 xd0 sdir# vss la19 la18 la17 sd15 sd14 sd13 sd12 sd11 sd10 vss sd9 sd8 vdd la23/idecs3# la22/idecs2# la21/idecs1# la20/idecs0# sa16 sa15 sa14 vss sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 vdd sa5 sa4 sa3 sa2 smwtc# smrdc# mw tc# mrdc# mr16# sbhe# m16# io16# romkbcs# irq8#osci rtcwr/idecyc# rt crd/psrstb# vdd int ignee# rtcale/pwrgd nmi ferr# vss wakeup0/idecyc#gcs wakeup1 osc vss pcirst# sioreq# serr# siognt# par plock# frame# irdy# trdy# devsel# stop# c/be3# c/be2# c/be1# c/be0# ad0 ad1
sis5503 pci system i/o preliminary v2.0 april 2, 1995 114 silicon integrated systems corporation 4.8.3 pin listing ( # means active low) 1=smwtc# 41=ad2 81=sa2 121=xd4 2=smrdc# 42=ad3 82=sa3 122=xd5 3=mwtc# 43=vdd 83=sa4 123=xd6 4=mrdc# 44=ad4 84=sa5 124=xd7 5=mr16# 45=ad5 85=vdd 125=eop 6=sbhe# 46=ad6 86=sa6 126=spkr 7=m16# 47=ad7 87=sa7 127=rfh# 8=io16# 48=ad8 88=sa8 128=zws# 9=romkbcs# 49=ad9 89=sa9 129=bale 10=irq8#/osci 50=ad10 90=sa10 130=iochk# 11=rtcwr/idecyc# 51=ad11 91=sa11 131=chrdy 12=rtcrd/psrstb# 52=ad12 92=sa12 132=aen 13=rtcale/pwrgd 53=ad13 93=sa13 133=iowc# 14=vdd 54=ad14 94=vss 134=iorc# 15=int 55=ad15 95=sa14 135=vdd 16=ignee# 56=ad16 96=sa15 136=bclk 17=nmi 57=ad17 97=sa16 137=irq1 18=ferr# 58=ad18 98=la20/idecs3# 138=irq3 19=vss 59=ad19 99=la21/idecs2# 139=irq4 20=wakeup0 /idecyc#/gcs 60=ad20 100=la22/idecs1# 140=irq5 21=wakeup1 61=ad21 101=la23/idecs0# 141=vss 22=osc 62=ad22 102=vdd 142=irq6 23=vss 63=ad23 103=sd8 143=irq7 24=pcirst# 64=ad24 104=sd9 144=irq9 25=sioreq# 65=ad25 105=vss 145=irq10 26=siognt# 66=ad26 106=sd10 146=irq11 27=serr# 67=ad27 107=sd11 147=irq12 28=par 68=vss 108=sd12 148=irq14 29=plock# 69=pciclk 109=sd13 149=irq15 30=frame# 70=ad28 110=sd14 150=rtcvdd 31=irdy# 71=ad29 111=sd15 151=dak2 32=trdy# 72=ad30 112=la17 152=dak1 33=devsel# 73=ad31 113=la18 153=dak0 34=stop# 74=intd# 114=la19 154=drq0 35=c/be3# 75=intc# 115=vss 155=drq1 36=c/be2# 76=intb# 116=sdir# 156=drq2 37=c/be1# 77=inta# 117=xd0 157=drq3 38=c/be0# 78=vss 118=xd1 158=drq5 39=ad0 79=sa0 119=xd2 159=drq6 40=ad1 80=sa1 120=xd3 160=drq7
sis5503 pci system i/o preliminary v2.0 april 2, 1995 115 silicon integrated systems corporation 4.8.4 pin description pci interface pin no. symbol type function 35-38 c/be[3:0]# i/o pci bus command and byte enables define the pci command during the address phase of a pci cycle, and the pci byte enables during the data phases. c/be[3:0]# are outputs when the 5503 is a pci bus master and inputs when it is a pci slave. 73-70 67-44 42-39 ad[31:0] i/o address and data are multiplexed on ad[31:0]. during the address phase of a transaction, ad[31:0] contains a physical address. during the data phase, ad[31:0] contains data. when the 5503 is a pci master, it drives address on ad[31:2] and drives ad[1:0] low during the address phase. during the data phase, it drives data or latches data on ad[31:0] for write or read cycle respectively. when the 5503 is a target, ad[31:0] are inputs during the address phase. during the data phases, the 5503 drives data on ad[31:0] for read cycle, or latches data for write cycle. 30 frame# i/o frame# is asserted to indicate the beginning of a bus transaction and asserted until the last data phase. when the pci master is ready to complete the final data phase, it deasserts frame#. when the 5503 is the target, frame# is an input to the 5503. 5503 drives frame# out when it is the pci master. frame# is tri-state during reset. 31 irdy# i/o when 5503 is the pci master, it drives irdy# to complete the current data phase of the transaction. during write cycles, the assertion of irdy# indicates the 5503 has driven valid data on ad[31:0]. during read cycles, it indicates the 5503 is ready to latch the data. irdy# is an input to the 5503 when the 5503 is the target and an output when the 5503 is a master.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 116 silicon integrated systems corporation 32 trdy# i/o trdy# is an output when the 5503 is a pci slave. the assertion of trdy# indicates the target agent's ability to complete the current data phase of the transaction. for a read cycle, trdy# indicates that the target has driven valid data onto the pci bus. for a write cycle, trdy# indicates that the target is prepared to accept data from the pci bus. when the 5503 is a pci master, trdy# is an input signal. 33 devsel# i/o the 5503 asserts devsel# when 5503's configuration registers or internal registers are addressed. devsel# is also asserted when the 5503 subtractively decodes a cycle. when 5503 is the pci master, devsel# is an input to indicate a pci target has responded to a 5503 initiated transaction. for all pci transactions, the 5503 also samples devsel# to decide to subtractively decode the cycle. 34 stop# i/o when the 5503 is a target it asserts stop# to request master to stop the current transaction. when 5503 is a master, the inputted stop# causes the 5503 to stop the current transaction. 28 par o par is even parity across ad[31:0] and c/be[3:0]# and regardless of whether or not all lines carry meaningful information. both address and data phases the par is generated. par is driven one pci clock after the corresponding address or data. par is driven by 5503 during the address phase of 5503 initiated transactions. during the data phase, 5503 also drives par when (1) 5503 is the master of a pci write transaction. (2) 5503 is the target of a read transaction. 27 serr# i the 5503 generates a nmi to the cpu when serr# is active. 29 plock# i the 5503 is locked when it samples plock# is negated during the address phase. any master attempt to access 5503 at this time, 5503 will initiate a retry to terminate th e transaction . the locked state lasts until 5503 samples both plock# and frame# are negated.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 117 silicon integrated systems corporation 69 pciclk i pciclk provides the fundamental timing and the internal operating frequency for the 5503. pciclk is a buffered input of 5501's pciclko. 24 pcirst# the pci reset brings 5503's registers, signals, etc. to a known state. 77-74 int[a:d]# i pci interrupt a to interrupt d. int[a:d]# can be remapped to one of eleven isa compatible interrupts, please refer to registers 41h to 44h for more detailed information. isa interface 97-95 93-86 84-79 sa[16:0] i/o system address. they are inputs when an external bus master is in control and are outputs at all other times. 114-112 la[19:17] i/o latched system address. they are inputs when an external bus master is in control and are outputs at all other times. 124-117 xd[7:0] i/o peripheral data bus lines. 111-106 104,103 sd[15:8] i/o system data bus are directly connected to the isa slots. 8 io16# i 16-bit i/o chip select indicates that the at bus cycle is a 16-bit i/o transfer when asserted or an 8-bit i/o transfer when it is negated. 7 m16# i 16-bit memory chip select indicates a 16-bit memory transfer when asserted or an 8-bit memory transfer when it is negated. 6 sbhe# i/o byte high enable signal indicates that the high byte has valid data on the isa 16-bit data bus. this signal is an output except during isa master cycles. 5 mr16# i master* is an active low signal from at bus. when active, it indicates that the isa bus master has the control of the system. the address and control signals are all driven by the isa bus master. 4 mrdc# i/o at bus memory read command signal is an output pin during at/dma/refresh cycles and is an input pin in isa master cycles. 3 mwtc# i/o at bus memory write command signal is an output pin during at/dma cycles and is an input pin in isa master cycles.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 118 silicon integrated systems corporation 2 smrdc# i/o at bus memory read. it instructs the memory devices to drive data onto the data bus. it is active only when the memory being accessed is within the lowest 1mb. 1 smwtc# i/o at bus memory write. it instructs the memory devices to store the data presented on the data bus. it is active only when the memory being accessed is within the lowest 1mb. 134 iorc# i/o at bus i/o read command signal is an output pin during at or dma cycles and is an input pin in isa master cycles. when low, it strobes an i/o device to place data on the data bus. 133 iowc# i/o at bus i/o write command signal is an output pin during at or dma cycles and is an input pin in isa master cycles. when low, it strobes data on the data bus into a selected i/o device. 132 aen o address enable is driven high on the isa bus to indicate the address lines are valid in dma or isa master cycles. it is low otherwise. 131 chrdy i/o i/o channel ready is normally high. it can be pulled low by the slow devices on the at bus to add wait states for the isa memory or i/o cycles. when a dma or an isa master accesses a vl- bus target, iordy is an output to control the wait states. 130 iochk# i i/o channel check is an active low input signal which indicates that an error has taken place on the i/o bus. 129 bale o bus address latch enable is used on the isa bus to latch valid address from the cpu. its falling edge starts the isa command cycles. 128 zws# i zero wait state is an active low signal. the system ignores the iordy signal and terminates the at bus cycle without additional wait state when it is asserted. 136 bclk i/o isa bus clock, for isa bus controller, isa bus interfaces and the dma controller. it can be programmed to derive from the sysclk or from the 14mhz clock.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 119 silicon integrated systems corporation 127 rfh# i/o refresh signal is used to initiate a refresh cycle. this signal is an input in isa bus master cycles and is an output in other cycles. 22 osc i osc is the buffered input of the external 14.318mhz oscillator. 125 eop o terminal count of dma. a pulse is generated by the dma controller when the terminal count (tc) of any channel reaches 1. when a tc pulse occurs, the dma controller will terminate the service, and if auto-initialize is enabled, the base registers will be written to the current registers of that channel. the mask bit and the tc bit in the status word will be set for the currently active channel unless the channel is programmed for auto-initialize. in that case, the mask bit remains clear. 160-154 drq7-5,3-0 i dma request inputs are used by external devices to indicate when they need service from the internal dma controllers. 137-140, 142,143, 144-149 irq1, 3-7, irq 9, 10-12,14,15 i these are the asynchronous interrupt request inputs to the 8259 controller. multi-function pins pin no. symbol type function 10 irq8#/osci i ? when using internal rtc: this pin is used as the time base of the built-in rtc. this signal is from the 32.768 khz crystal oscillator. ? when using external rtc: this pin is used as irq8#, which is the asynchronous interrupt request input to the 8259 controller. 12 rtcrd/psrst b# i/o ? when using internal rtc: this signal is used as psrstb# (power strobe). psrstb# establishes the condition of the control register in rtc when power is first applied to the device. ? when using external rtc: the signal is used as the data read strobe of rtc. it is used to drive the rtc data onto the xd bus when the cpu accesses the rtc.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 120 silicon integrated systems corporation 11 rtcwr/idecy c# o ? when using internal rtc or super i/o device's rtc: this pin is used as idecyc#(ide cycle indicator). ? when using external rtc: this pin is used as data write strobe of rtc. it is used to store the data presented on the xd bus when cpu accesses the rtc. this pin must be connected to the r/w pin of rtc. 13 rtcale/pwrg d i/o ? when using internal rtc: the signal must be high for bus cycles in which the cpu accesses the rtc. all address, data, data strobe, and r/w pins of the internal rtc are disconnected from the processor when this signal is low. ? when using external rtc: the signal is used to latch the address from the xd bus when cpu accesses rtc. 20 wakeup0/ide cyc#/gcs o ? when using internal rtc: the signal is directly connected to the 5501 when it is used as wakeup0. when activated, it will reload the monitor standby timer. if it is inactive and the monitor standby timer expires, the system will enter into monitor standby state. during the monitor standby state, if this input become active, the system will wake up from standby state and return back to normal state. this pin can also be used to issue a logical high write signal with pulse width equal to iowc#, and at this time the wakeup0 function doesn't exist any longer. this function can be enabled by setting bit 4 of i/o port 22h index 80h. once it is enabled, the write pulse is generated by writing index register 82h. ? when using external rtc and internal ide: this pin is used as idecyc# 101-98 la[23:20]/idec s[3:0]# i/o normally, these signals are isa latched system address. when idecyc# is asserted, they become ide chip select signals. latched system address. they are inputs when an external bus master is in control and are outputs at all other times. others
sis5503 pci system i/o preliminary v2.0 april 2, 1995 121 silicon integrated systems corporation 151-153 dak[2:0] o the dak output lines indicate that a request for dma service has been granted by the 5503 or that a 16 bit master has been granted the bus. one external 74138 decodes these signals to dak[7:0] for the corresponding peripheral. 150 rtcvdd battery power for rtc 25 sioreq# o sio request. the 5503 sioreq# to request the pci bus. 26 siognt# i sio grant. it is driven by the 5501 to indicate that the pci arbiter has granted the use of the pci bus to the 5503. 9 romkbcs# o keyboard or system rom chip select 126 spkr o speaker is the output for the speaker . 116 sdir# o sd low byte data direction controls the direction of the low byte buffer between sd and xd. a high sets the data path direction from xd to sd and a low sets the data path direction from sd to xd. 21 wakeup1 o this signal is directly connected to the 5501. when activated, it will reload the system standby timer. if it is inactive and the system standby timer expires, the system will enter into system standby state. during the system standby state, if this input become active, the system will wake up from standby state and return back to normal state. 18 ferr# i floating point error from the cpu. it is driven active when a floating point error occurs. 16 ignee# od ignee# is normally in high impedance state, and is asserted to inform cpu to ignore a numeric error. a resistor connected to either 3.3v (for p54c) or 5v (p5) is required to maintain a correct voltage level to cpu. 17 nmi od non-maskable, interrupt is rising edge trigger signal to the cpu and is generated to invoke a non-maskable interrupt. normally, this signal is low. it goes high impedance state when a non-maskable interrupt source comes up. an external pull up resistor is required to be directly connected to cpu. 15 int od interrupt goes high impedance whenever a valid interrupt request is asserted. hence, an external pull up resister is required to be directly connected to the cpu's interrupt pin.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 122 silicon integrated systems corporation 14,43,85 102,135 vdd +5v dc power 19,23,68 78,94,105 115,141 vss ground
sis5503 pci system i/o preliminary v2.0 april 2, 1995 123 silicon integrated systems corporation 4.9 electrical characteristics 4.9.1 absolute maximum ratings parameter min max unit ambient operating temperature 0 70 o c storage temperature -40 125 o c input voltage -0.3 5.5 v output voltage -0.5 5.5 v power dissipation 1 w note: stress above these listed may cause permanent damage to device. functional operation of this device should be restricted to the conditions described under operating conditions. 4.9.2 dc characteristics ta = 0 - 70 o c, vss = 0v , vdd=5v+5% symbol parameter min max unit condition v il input low voltage -0.3 0.8 v v ih input high voltage v v ol output low voltage 0.45 v v oh output high voltage 2.4 v i ol1 output low current 4 ma note 1 i oh1 output high current 4 ma note 1 i ol2 output low current 8 ma note 2 i oh2 output high current 8 ma note 2 i ol3 output low current 8,12 ma note 3 i oh3 output high current 8,12 ma note 3 i ol4 output low current 6 ma note 4 i oh4 output high current 6 ma note 4 i il input leakage current +10 ma i ol output leakage current -10 ma c in input capacitance 12 pf c out output capacitance 12 pf c i/o i/o capacitance 12 pf note: 1. i ol1 and i oh1 are applicable to romkbcs#, rtcwr/idecyc#, rtcrd/psrstb#, rtcale/pwrgd, wakeup0/idecyc#/gcs, wakeup1, sioreq#, par, c/be3#, c/be2#, c/be1#, c/be0#, ad[31:0], sdir#, xd[7:0], spkr, bclk, dak[2:0], int, nmi, ignee#.
sis5503 pci system i/o preliminary v2.0 april 2, 1995 124 silicon integrated systems corporation 2. i ol2 and i oh2 are applicable to rfh#, chrdy, aen, bale, eop, sd[15:8]. 3. i ol3 and i oh3 are applicable to smwtc#, smrdc#, mwtc#, mrdc#, sbhe#, la[23:20]/idecs[3:0]#, la[21:17], sa[16:0], iowc#, iorc#. please refer to register description. 4. i ol4 and i oh4 are applicable to frame#, irdy#, trdy#, devsel#, stop#. 4.9.3 ac characteristics the ac characteristic is measured under the following capacitive condition. capacitive load pin 35pf bclk, dak[0:2], bale, aen, nmi, sdir, eop, spkr, int 50pf` frame#, irdy#, trdy#, devsel#, stop#, c/be[3:0]#, xd[7:0] 150pf sd[15:8], sbhe#, rfh#, chrdy, mwtc#, mrdc#, iorc#, iowc#, sa[19:0], la[23:17] para- meter description min typ max unit isa bus interface signals ( figure 4.2) bclk high 63.2 ns bclk low 56.8 ns t1 bale valid delay from bclk 4.5 7 ns t2 iorc#, iowc#, mrdc#, mwtc# valid delay from bclk 16.5 24 ns t3 iorc#, iowc#, mrdc#, mwtc# invalid delay from bclk 12 18 ns t5a m16# setup time to bclk rising 15 ns t5b m16# hold time from bclk rising 6 ns t6a io16# setup time to bclk falling 19 ns t6b io16# hold time from bclk falling 6 ns t7 16 bit iorc#, iowc# pulse width 1.5 bclk 8 bit iorc#, iowc# pulse width 4.5 bclk 16 bit mrdc#, mwtc# *1 2 bclk 8 bit mrdc#, mwtc# 4.5 bclk rom mrdc#, mwtc# *1 2 bclk data buffer interface t8 sd, xd data set up time to iorc#, mrdc# inactive 10 ns t9 sd, xd data hold time to iorc#, mrdc# inactive 3ns t10 sd, xd valid data delay from iowc#, 15 22 ns mwtc# active ( for data swapping)
sis5503 pci system i/o preliminary v2.0 april 2, 1995 125 silicon integrated systems corporation t11a sd, xd data hold time from iowc#, mwtc# inactive in write disassembly cycle 15 22 ns t11b sd, xd data hold time from iowc#, mwtc# inactive in write cycle 172 ns t12 sd, xd valid to iowc#, mwtc# active 142 ns t13 sdir deassertion to iorc#, mrdc# active ( 16 bit) 12bclk sdir deassertion to iorc#, mrdc# active ( 8 bit) 1.5 2.5 bclk t14 sdir assertion delay from iorc#, mrdc# inactive 2bclk address buffer interface t15 sa, la propagation delay from pciclk in frame# address phase 34 51 ns t16 sa0, sa1, sbhe# hold time from the negation of iorc#, iowc#, mwtc#, mrdc# 10 ns t17a chrdy setup time to bclk rising 15.2 ns t17b chrdy hold time to bclk rising 14.8 ns t44 zws# setup time to bclk faling 10 ns t45 zws# hold time to bclk faling 20 ns dma compatible timings ( figure 4.3, 4.4) t18 dak active to iorc# active 0.5 dmaclk t19 dak acive to iowc# active 1.5 dmaclk t20 dak active hold from iorc# inactive 0.5 dmaclk t21 dak active hold from iowc# inactive 0.5 dmaclk t22a aen active to iorc# active 6 dmaclk t22b aen active to iowc# active 7 dmaclk t23a aen inactive from iorc# inactive 3 dmaclk t23b aen inactive from iowc# inactive 4 dmaclk t24a bale active to iorc# active 1.5 dmaclk t24b bale active to iowc# active 2.5 dmaclk t25a bale inactive from iorc# inactive 1 dmaclk t25b bale inactive from iowc# inactive 1 dmaclk t26a la, sa, sbhe# valid set up time to iorc# 1dmaclk t26b la, sa, sbhe# valid set up time to iowc# 2dmaclk t27a la, sa, sbhe# valid hold from iorc# 0.5 dmaclk
sis5503 pci system i/o preliminary v2.0 april 2, 1995 126 silicon integrated systems corporation t27b la, sa, sbhe# valid hold from iowc# 0.5 dmaclk t28 iorc# pusle width 4 dmaclk t29 iowc# pusle width 2 dmaclk t30 mrdc# pusle width 3 dmaclk t31 mwtc# pusle width 3 dmaclk t32 mwtc# active from iorc# active 1 dmaclk t33 iowc# active from mrdc# active 1 dmaclk t34 mwtc# inactive from iorc# inactive 0 ns t35 iowc# inactive from mrdc# inactive 1.5 ns t36 read data valid from iorc# active 267.5 ns t37 read data valid hold from iorc# inactive 32.2 ns t38 write data valid setup to iowc# inactive 162.5 ns t39 write data valid hold from iowc# inactive 13.2 ns t40 eop active delay from iowc# active -7.6 ns t41 eop active delay from iorc# active 112.3 ns t42 eop active delay from iowc# inactive 0.7 ns t43 eop active delay from iorc# inactive 0.8 ns note: dmaclk = bclk or bclk/2 depends on bit 0 of isa configuration register 01h. refresh timing (figure 4.13) t44 rfh# active setup to mrdc# active 2 bclk t45 rfh# active hold from mrdc# inactive 0.5 bclk t46 aen active to rfh# active delay 3 ns miscellaneous timing ( figure 4.5 ~ 4.9, 4.11, 4.12) t47 serr#, iochk# active to nmi output floating active 200 ns t48 int output floating delay from irq active 100 ns t49 irq active pulse width 100 ns t50 ignee# active from iowc# active for port f0h access 220 ns t51 ignee# inactive from ferr# inactive 150 ns t52 spkr valid delay from osc timing 200 ns t53 rtcale pulse width 532.3 ns t54 rtcale active from iorw# active 4 ns t54a rtcwr active from iowr# active 5 ns t54b rtcrd active from iord# active 5 ns t54c rtcwr inactive from iowr# inactive 3.5 5 10 ns
sis5503 pci system i/o preliminary v2.0 april 2, 1995 127 silicon integrated systems corporation t54d rtcrd inactive from iord# inactive 3.5 5 10 ns *1: no command delay pci bus ac specifications ( figure 4.10) the following parameters are applicable to ad[31:0], c/be[3:0], frame#, trdy#, irdy#, stop#, lock#, idsel#, devsel#, par, and serr#. min typ max units t57 signal valid delay from pciclk rising edge *2 11 ns t58 signal invalid delay from pciclk rising edge 2ns t59 hi-impedance to active delay from pciclk rising edge 2ns t60 active to hi-impedance delay from pciclk rising edge 28 ns t61 setup time of input signal 7 ns t62 hold time of input signal 0 ns *2: this parameter is measured under 50pf. pci ide timing ( figure 4.14 ~ 4.17) para- meter description min typ max unit t63 read active time 3 8 pciclk t64 read recovery time 3 13 pciclk t65 write active time 4 8 pciclk t66 write recovery time 5 17 pciclk t67 read cycle tme (prefetch buffer enable) 45 pciclk t68 write cycle time (post write buffer enable) 6 pciclk
sis5503 pci system i/o preliminary v2.0 april 2, 1995 128 silicon integrated systems corporation 4.9.4 ac timing diagram pci clk fr a m e # ir d y # trd y# devsel# c/ be# ad bclk bale io r c # /i ow c# mrdc#/mw tc# sd i r ch rd y la , sa sd , xd ( io r c # , mrdc# ) sd , xd ( io w c # , mw tc# ) m16# sd , xd ( io w c # , mw tc# ) * 1 sb h e# sa 1 , 0 zw s# io 1 6 # figure 4.2 pci to at bus cycle
sis5503 pci system i/o preliminary v2.0 april 2, 1995 129 silicon integrated systems corporation ad fr a m e # ir d y # trd y# sio r eq # sio g n t# bclk aen bale drq dak io r c # m w tc# eo p la , sa sd , xd dma cycle (iowc#, mrdc#), dmaclk = bclk figure 4.3 dma cycle (iowc#, mrdc#)
sis5503 pci system i/o preliminary v2.0 april 2, 1995 130 silicon integrated systems corporation ad fr a m e # ir d y # trd y# sio r eq # sio g n t# bclk aen bale drq dak io w c # mrdc# eo p la , sa sd , x d dma cycle (iorc#, mwtc#), dmaclk = bclk figure 4.4 dma cycle (iorc#, mwtc#)
sis5503 pci system i/o preliminary v2.0 april 2, 1995 131 silicon integrated systems corporation ser r# nm i t47 io c h k # figure 4.5 t48 t49 ir q x ir q x in t figure 4.6 t50 t51 fer r # ir q 1 3 io w c # ( w rite f0h) ignee# figure 4.7 t52 osc spkr figure 4.8 t54 t53 io w c # rtcale figure 4.9
sis5503 pci system i/o preliminary v2.0 april 2, 1995 132 silicon integrated systems corporation 1.5v t57 pciclk o u tpu t sig n a l in p u t sig n a l t58 t59 t60 t61 t62 t ri-state output figure 4.10 t54a io w c # rtcw r t54c figure 4.11 t54b io r c # rtcrd t54d figure 4.12 aen rfh # mrdc# t44 t45 t46 figure 4.13
sis5503 pci system i/o preliminary v2.0 april 2, 1995 133 silicon integrated systems corporation t65 t65 cbe ad pciclk frame# irdy# c/be# ad[31:0] trdy# devsel# par iorc# iowc# data[15:0] address[2:0] idecyc# figure 4.14 ide basic write cycle (one word) t67 t63 t63 t64 cbe a cbe pard pard ad d pciclk frame# irdy# c/be# ad[31:0] trdy# devsel# par iorc# iowc# data[15:0] address[2:0] idecyc# figure 4.15 ide read-prefetch cycle (one word)
sis5503 pci system i/o preliminary v2.0 april 2, 1995 134 silicon integrated systems corporation t63 t63 cbe a d pciclk frame# irdy# c/be# ad[31:0] trdy# devsel# par iorc# iowc# data[15:0] address[2:0] idecyc# figure 4.16 ide basic read cycle (one word) t68 t68 t65 t65 t66 cbe ad pciclk frame# irdy# c/be# ad[31:0] trdy# devsel# par iorc# iowc# data[15:0] address[2:0] idecyc# figure 4.17 ide posted-write cycle (double words)
pentium/p54c pci/isa chipset preliminary v2.0 april 2, 1995 135 silicon integrated systems corporation 5. mechanical dimension 5.1 sis5501, SIS5502 (208 pins) qfp208-p (208-pin plastic flat package) unit:mm 156 28.0+ 0.2 30.6+ 0.3 105 1 1.25typ 208 52 0.08 m 53 157 0.5+ 0.1 0.2+ 0.1 104 0.5+ 0.2 0.1 29.6+ 0.3
pentium/p54c pci/isa chipset preliminary v2.0 april 2, 1995 136 silicon integrated systems corporation 5.2 sis5503 (160 pins) qfp160-p (160-pin plastic flat package) unit:mm 28.0+ 0.2 31.2+ 0.4 1.325typ 0.65+ 0.1 0.3+ 0.1 29.6+ 0.4 120 80 40 160 1 0.8+ 0.2
pentium/p54c pci/isa chipset preliminary v2.0 april 2, 1995 137 silicon integrated systems corporation copyright notice ` copyright 1995, silicon integrated systems corp. all rights reserved. this manual is copyrighted by silicon integrated systems corp. you may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without the express written permission of silicon integrated systems corp. trademarks sis is a registered trademark of silicon integrated systems corp. all brands or product names mentioned are trademarks or registered trademarks of their respective holders. disclaimer silicon integrated systems corp. makes no representations or warranties regarding the contents of this manual. we reserve the right to revise the manual or make changes in the specifications of the product described within it at any time without notice and without obligation the notify any person of such revision or change. the information contained in this manual is provided for general use by our customers. our customers should be aware that the personal computer field ins the subject of many patents. our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. it is the policy of silicon integrated systems corp. to respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights. restricted rights legend use, duplication, or disclosure by the government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the rights in technical data and computer software clause at 252.277-7013.

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